Alternatives and similar repositories for abc_py

Users that are interested in abc_py are comparing it to the libraries listed below

• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆29Updated 5 years ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆144Updated 6 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆30Updated 3 years ago
• TimingPredict / TimingPredict
  Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)
  ☆88Updated last year
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• zshi0616 / DeepGate2
  ☆31Updated 2 years ago
• lnis-uofu / ML-Mapper
  ☆13Updated 3 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆80Updated 2 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆62Updated 7 months ago
• MIRALab-USTC / AI4EDA-EfficientPlace
  This is the code for our paper "Reinforcement Learning within Tree Search for Fast Macro Placement".
  ☆34Updated last year
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆56Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆157Updated 3 weeks ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆26Updated 3 years ago
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆27Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• TimingPredict / Dataset
  Timing prediction dataset download and instructions.
  ☆17Updated 2 years ago
• laiyao1 / maskplace
  ☆68Updated last month
• IntelLabs / FloorSet
  ☆81Updated last month
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆66Updated 8 months ago
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆56Updated 2 years ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆76Updated 3 weeks ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆142Updated 2 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• ABKGroup / TritonRoute-WXL
  ☆36Updated 5 years ago