lydiawunan / LOSTIN
LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
☆17Updated 2 years ago
Related projects: ⓘ
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…☆37Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆45Updated 2 months ago
- GNN-RE datasets for circuit recognition☆37Updated last year
- ☆18Updated 4 months ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆43Updated 3 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆16Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆25Updated 3 years ago
- ☆14Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆58Updated 3 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆28Updated 3 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆107Updated last month
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated 10 months ago
- ☆39Updated 2 months ago
- IronMan+alpha: Graph Neural Network and Reinforcement Learning in High-Level Synthesis☆23Updated 2 years ago
- ☆14Updated 3 years ago
- Approximation-Aware Functional Reverse Engineering using Graph Neural Networks☆9Updated last year
- Awesome machine learning for logic synthesis☆23Updated last year
- Problems and Results of IWLS 2023 Programming Contest☆14Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆9Updated 3 months ago
- Simple Python interface for ABC☆21Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆16Updated 3 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆54Updated 5 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆15Updated 2 months ago
- ☆29Updated 11 months ago
- ☆15Updated 2 years ago
- ☆24Updated 9 months ago
- GPU-based logic synthesis tool☆65Updated 2 months ago
- Artificial Netlist Generator☆29Updated 6 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆17Updated 11 months ago
- Graph Neural Networks for Predicting Circuit Reliability Degradation. TCAD 2022☆16Updated last year