panhomyoung / phyLSLinks
A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
☆28Updated last month
Alternatives and similar repositories for phyLS
Users that are interested in phyLS are comparing it to the libraries listed below
Sorting:
- Research paper based on or related to ABC.☆44Updated 2 weeks ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆49Updated 5 months ago
- ☆22Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 3 weeks ago
- ☆28Updated last year
- GPU-based logic synthesis tool☆81Updated 11 months ago
- A logic synthesis tool☆74Updated this week
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- The first version of TritonPart☆27Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Pin-Accessible Legalization for Mixed-Cell-Height Circuits☆29Updated 3 years ago
- IDEA project source files☆106Updated 7 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 6 months ago
- Artificial Netlist Generator☆39Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆19Updated 2 months ago
- Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS☆42Updated 7 months ago
- ☆38Updated 2 years ago
- ☆23Updated 7 months ago
- Problems and Results of IWLS 2022 Programming Contest☆19Updated 2 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆31Updated 7 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆30Updated 2 weeks ago
- Timing prediction dataset download and instructions.☆15Updated 2 years ago
- ☆30Updated 4 years ago
- ☆18Updated 2 years ago
- ☆25Updated last year
- ☆9Updated 3 years ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆127Updated this week