panhomyoung / phyLSLinks
A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
☆39Updated last month
Alternatives and similar repositories for phyLS
Users that are interested in phyLS are comparing it to the libraries listed below
Sorting:
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- EPFL logic synthesis benchmarks☆227Updated 2 months ago
- ☆27Updated last year
- Research paper based on or related to ABC.☆70Updated 3 weeks ago
- A logic synthesis tool☆84Updated 5 months ago
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- GPU-based logic synthesis tool☆97Updated 2 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66Updated 8 months ago
- ☆31Updated 2 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Updated last year
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Updated 4 years ago
- The first version of TritonPart☆31Updated 2 years ago
- Artificial Netlist Generator☆46Updated last year
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆30Updated 6 years ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- IDEA project source files☆111Updated 3 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆169Updated 9 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆79Updated 7 months ago
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆156Updated 3 weeks ago
- ☆42Updated 3 years ago
- ☆19Updated 5 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆137Updated last year
- Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)☆88Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆107Updated 7 months ago
- ☆95Updated 7 months ago
- ☆29Updated 4 months ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated 3 weeks ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- CUGR, VLSI Global Routing Tool Developed by CUHK☆142Updated 2 years ago