Alternatives and similar repositories for phyLS

Users that are interested in phyLS are comparing it to the libraries listed below

• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆48Updated 4 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆43Updated last week
• zshi0616 / python-deepgate
  ☆22Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 10 months ago
• nbulsi / also
  A logic synthesis tool
  ☆73Updated last month
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆14Updated 3 years ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆48Updated this week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆106Updated 6 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆26Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆39Updated last year
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆18Updated last month
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆51Updated 4 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆28Updated 3 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 5 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆19Updated 2 years ago
• geziangfinn / easyPlace
  Reimplementation of the VLSI placement algorithm: ePlace and ePlace-MS
  ☆39Updated 7 months ago
• abk-openroad / BST-DME
  Bounded-Skew DME v1.3
  ☆14Updated 6 years ago
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated last month
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆26Updated 2 years ago
• mgwoo / RePlAce
  ☆9Updated 3 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆19Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• ECASLab / AxLS
  AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis
  ☆10Updated last week
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆30Updated 7 months ago