Alternatives and similar repositories for hdl-benchmarks

Users that are interested in hdl-benchmarks are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆107Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last week
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆58Updated 10 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• zshi0616 / python-deepgate
  ☆26Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• NVlabs / INSTA
  ☆89Updated 5 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆88Updated 7 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated 11 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆110Updated last month
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆62Updated 3 weeks ago
• IntelLabs / FloorSet
  ☆77Updated 5 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆29Updated last year
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆38Updated 4 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆220Updated 3 weeks ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆103Updated 5 months ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆66Updated 6 months ago
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆44Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆82Updated 3 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated 6 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆133Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆40Updated 3 years ago
• pkuzjx / eda-collection
  ☆107Updated 6 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆52Updated last year
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆139Updated 2 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆42Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago