A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
☆72Apr 30, 2026Updated last week
Alternatives and similar repositories for Benchmarks
Users that are interested in Benchmarks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆70May 14, 2025Updated 11 months ago
- EPFL logic synthesis benchmarks☆245Mar 3, 2026Updated 2 months ago
- Collection of digital hardware modules & projects (benchmarks)☆97Feb 27, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 3 years ago
- ☆29Jun 25, 2024Updated last year
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆29Oct 17, 2020Updated 5 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆148Jul 23, 2025Updated 9 months ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 11 months ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 3 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- VGA LCD Core (OpenCores)☆15May 22, 2018Updated 7 years ago
- ☆17May 24, 2023Updated 2 years ago
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆32Sep 19, 2025Updated 7 months ago
- ☆20Oct 27, 2022Updated 3 years ago
- DeepGate3 for ICCAD2024☆14May 26, 2025Updated 11 months ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 10 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆118May 18, 2023Updated 2 years ago
- ☆10Dec 12, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Updated this week
- ☆14Jun 12, 2024Updated last year
- ☆14Oct 8, 2024Updated last year
- Combinational ATPG generator based on D-Algorithm☆16Nov 25, 2020Updated 5 years ago
- Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements☆28Dec 16, 2020Updated 5 years ago
- AIGER And-Inverter-Graph Library☆101Feb 17, 2026Updated 2 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆111Jul 2, 2025Updated 10 months ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆1,160Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- The Berkeley Verilog-A Parser and Processor☆15Mar 24, 2017Updated 9 years ago
- ☆33Dec 2, 2023Updated 2 years ago
- ☆13Feb 6, 2021Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- ☆19Jul 2, 2024Updated last year
- ☆17Jul 16, 2020Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago