A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
☆67Jan 13, 2025Updated last year
Alternatives and similar repositories for Benchmarks
Users that are interested in Benchmarks are comparing it to the libraries listed below
Sorting:
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Dec 3, 2021Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆67May 14, 2025Updated 9 months ago
- EPFL logic synthesis benchmarks☆231Nov 18, 2025Updated 3 months ago
- Collection of digital hardware modules & projects (benchmarks)☆85Feb 27, 2026Updated last week
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆29Oct 17, 2020Updated 5 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- ☆27Jun 25, 2024Updated last year
- ☆15May 24, 2023Updated 2 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Power grid analysis☆20Aug 5, 2020Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆20Oct 27, 2022Updated 3 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66May 29, 2025Updated 9 months ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆117May 18, 2023Updated 2 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆108Jul 2, 2025Updated 8 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- ☆14Jun 12, 2024Updated last year
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- ☆10Dec 12, 2023Updated 2 years ago
- DeepGate3 for ICCAD2024☆13May 26, 2025Updated 9 months ago
- VGA LCD Core (OpenCores)☆14May 22, 2018Updated 7 years ago
- ☆14Feb 3, 2025Updated last year
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 8 months ago
- Optimization results for superconducting electronic (SCE) circuits☆18Dec 5, 2023Updated 2 years ago
- symmetric clock tree synthesis for NTV IC design☆11May 8, 2022Updated 3 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 3 years ago
- GNN-RE datasets for circuit recognition☆56May 16, 2023Updated 2 years ago
- ☆32Dec 2, 2023Updated 2 years ago
- Simple Python interface for ABC☆29May 19, 2023Updated 2 years ago
- Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements☆28Dec 16, 2020Updated 5 years ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Jul 26, 2023Updated 2 years ago
- This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).☆30Sep 19, 2025Updated 5 months ago