Alternatives and similar repositories for Benchmarks

Users that are interested in Benchmarks are comparing it to the libraries listed below

• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆75Updated last month
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆62Updated 7 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated 3 weeks ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 3 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆224Updated last month
• NVlabs / INSTA
  ☆91Updated 6 months ago
• zshi0616 / python-deepgate
  ☆27Updated last year
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆104Updated 6 months ago
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆66Updated 8 months ago
• nbulsi / also
  A logic synthesis tool
  ☆84Updated 4 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• IntelLabs / FloorSet
  ☆78Updated last week
• ASU-VDA-Lab / 2024_ICCAD_Contest_Gate_Sizing_Benchmark
  ☆25Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆108Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆91Updated 8 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆167Updated 8 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆65Updated 2 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• CODA-Team / AnalogGym
  ☆72Updated 2 months ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆141Updated 2 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆136Updated last year
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆54Updated last year
• ABKGroup / PROBE3.0
  ☆49Updated last year
• bluesceada / iscas89_hl_verilog
  Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
  ☆15Updated 4 years ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆60Updated 7 months ago
• tsung-wei-huang / ece5960-physical-design
  ☆42Updated 3 years ago