Alternatives and similar repositories for percy

Users that are interested in percy are comparing it to the libraries listed below

• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆36Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆26Updated 2 years ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆44Updated 3 weeks ago
• nbulsi / also
  A logic synthesis tool
  ☆74Updated last week
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆27Updated 5 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆28Updated this week
• lnis-uofu / LSOracle
  IDEA project source files
  ☆106Updated 7 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆19Updated 2 months ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆14Updated last year
• amahzoon / genmul
  ☆16Updated 4 years ago
• SPbSAT / cirbo
  ☆22Updated 2 weeks ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated this week
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated 11 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆50Updated 5 months ago
• lsils / bill
  C++ header-only reasoning library
  ☆16Updated 11 months ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆19Updated 2 months ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆49Updated 7 months ago
• Ravenslofty / librecell
  ☆24Updated 4 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆58Updated last year
• pulp-platform / ELAU
  ☆18Updated last year
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆24Updated 5 months ago