Alternatives and similar repositories for percy:

Users that are interested in percy are comparing it to the libraries listed below

• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆35Updated 7 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆24Updated 2 years ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆14Updated 8 years ago
• lsils / bill
  C++ header-only reasoning library
  ☆13Updated 6 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆21Updated 3 weeks ago
• amahzoon / genmul
  ☆14Updated 4 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆17Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆37Updated 2 months ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆12Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆72Updated 2 years ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆102Updated 2 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆24Updated 2 weeks ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆27Updated 6 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆23Updated 9 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆79Updated 6 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆41Updated 2 weeks ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆16Updated 4 months ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆192Updated 9 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated last month
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆16Updated 4 years ago
• msoeken / kitty
  C++ truth table library
  ☆51Updated 10 months ago
• msoeken / cirkit
  A circuit toolkit
  ☆96Updated 4 years ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆25Updated 2 years ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆29Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆39Updated 4 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆50Updated last year
• lsils / mockturtle
  C++ logic network library
  ☆221Updated 3 months ago