Benchmarks for Approximate Circuit Synthesis
☆17Aug 2, 2020Updated 5 years ago
Alternatives and similar repositories for BACS
Users that are interested in BACS are comparing it to the libraries listed below
Sorting:
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆32Nov 13, 2023Updated 2 years ago
- ABACUS is a tool for approximate logic synthesis☆14Jul 13, 2020Updated 5 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Dec 23, 2024Updated last year
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆13Sep 14, 2025Updated 6 months ago
- EPFL logic synthesis benchmarks☆233Mar 3, 2026Updated 2 weeks ago
- DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)☆117May 18, 2023Updated 2 years ago
- Library of approximate arithmetic circuits☆62Jan 14, 2026Updated 2 months ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Code of "Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures", TCAD 2020☆13Apr 1, 2021Updated 4 years ago
- A copy of the latest version of MVSIS☆12Apr 18, 2021Updated 4 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 3 years ago
- C++ header-only reasoning library☆16Jul 11, 2024Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆85Feb 27, 2026Updated 3 weeks ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 3 years ago
- ☆31Oct 2, 2023Updated 2 years ago
- A logic synthesis tool☆86Sep 8, 2025Updated 6 months ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆25Jul 12, 2023Updated 2 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- IDEA project source files☆112Oct 15, 2025Updated 5 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 4 months ago
- Showcase examples for EPFL logic synthesis libraries☆203Apr 5, 2024Updated last year
- VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis☆13Mar 8, 2022Updated 4 years ago
- EDA physical synthesis optimization kit☆64Nov 13, 2023Updated 2 years ago
- DATC RDF☆49Jul 31, 2020Updated 5 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆28Dec 23, 2025Updated 2 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆41Aug 15, 2025Updated 7 months ago
- Datasets for EDA LLM research☆38Jan 17, 2025Updated last year
- The Verilog source code for DRUM approximate multiplier.☆32May 4, 2023Updated 2 years ago
- C Socket Programming for Linux with a Server and Client Example Code☆10Jan 5, 2022Updated 4 years ago
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- An open-source Simulation Trace Format specification☆15Nov 12, 2025Updated 4 months ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆14Oct 11, 2024Updated last year
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- ☆19Dec 21, 2020Updated 5 years ago