jpsety / verilog_benchmark_circuitsLinks
EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
☆29Updated 5 years ago
Alternatives and similar repositories for verilog_benchmark_circuits
Users that are interested in verilog_benchmark_circuits are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆74Updated this week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆58Updated 10 months ago
- A logic synthesis tool☆82Updated 3 months ago
- IDEA project source files☆110Updated last month
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆103Updated 5 months ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Updated 4 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- DATC RDF☆50Updated 5 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆38Updated 4 months ago
- ☆29Updated last year
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆66Updated 6 months ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆88Updated 7 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆38Updated 3 months ago
- ☆107Updated 6 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆107Updated last year
- EDA physical synthesis optimization kit☆63Updated 2 years ago
- Research paper based on or related to ABC.☆62Updated last month
- GPU-based logic synthesis tool☆97Updated 2 weeks ago
- EPFL logic synthesis benchmarks☆220Updated 3 weeks ago
- VLSI EDA Global Router☆77Updated 7 years ago
- ☆18Updated 4 years ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- ☆26Updated last year
- DATC Robust Design Flow.☆36Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆95Updated last year
- This is a python repo for flattening Verilog☆20Updated 6 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Updated 8 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 8 months ago