EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
☆31Jan 17, 2020Updated 6 years ago
Alternatives and similar repositories for verilog_benchmark_circuits
Users that are interested in verilog_benchmark_circuits are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆16Dec 3, 2021Updated 4 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆71Jan 13, 2025Updated last year
- EPFL logic synthesis benchmarks☆234Mar 3, 2026Updated 3 weeks ago
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆26Apr 9, 2025Updated 11 months ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- ☆33Dec 2, 2023Updated 2 years ago
- Problems and Results of IWLS 2023 Programming Contest☆17Apr 12, 2025Updated 11 months ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆23May 24, 2025Updated 10 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- ☆15May 24, 2023Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆25Jul 12, 2023Updated 2 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- GNN-RE datasets for circuit recognition☆57May 16, 2023Updated 2 years ago
- SIMPLER MAGIC: Synthesis and In-memory MaPping of Logic Execution in a single Row for Memristor Aided loGIC☆13Dec 5, 2019Updated 6 years ago
- ☆28Jun 25, 2024Updated last year
- ☆13Dec 31, 2022Updated 3 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- A synthesis flow for hybrid processing-in-RRAM modes☆12Jul 15, 2021Updated 4 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆87Feb 27, 2026Updated 3 weeks ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- ABC: System for Sequential Logic Synthesis and Formal Verification☆32Mar 9, 2026Updated 2 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆67May 29, 2025Updated 9 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆29Jan 21, 2025Updated last year
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆13Sep 14, 2025Updated 6 months ago
- AIGER And-Inverter-Graph Library☆98Feb 17, 2026Updated last month
- Optimization results for superconducting electronic (SCE) circuits☆18Dec 5, 2023Updated 2 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated 11 months ago
- A circuit toolkit☆107Feb 23, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- C++ header-only exact synthesis library☆17Jan 18, 2023Updated 3 years ago
- ☆14Aug 27, 2020Updated 5 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 8 months ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- Niklas Een's ABC/ZZ framework☆24May 14, 2022Updated 3 years ago
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- Tools for working with circuits as graphs in python☆127Nov 17, 2023Updated 2 years ago