nbulsi / alsoLinks
A logic synthesis tool
☆81Updated last week
Alternatives and similar repositories for also
Users that are interested in also are comparing it to the libraries listed below
Sorting:
- EPFL logic synthesis benchmarks☆211Updated 2 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆34Updated 2 months ago
- IDEA project source files☆108Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆61Updated last week
- GPU-based logic synthesis tool☆90Updated last month
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆56Updated 8 months ago
- Showcase examples for EPFL logic synthesis libraries☆197Updated last year
- Research paper based on or related to ABC.☆52Updated 2 months ago
- C++ logic network library☆250Updated last month
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Rsyn – An Extensible Physical Synthesis Framework☆129Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆155Updated 4 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 8 months ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 5 months ago
- ☆23Updated last year
- DATC RDF☆50Updated 5 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆177Updated 4 months ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- UCSD Detailed Router☆90Updated 4 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 4 months ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Updated 7 years ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆94Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆54Updated 3 months ago
- ☆29Updated last year
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆17Updated 2 years ago
- ☆17Updated 4 years ago
- ☆34Updated 4 years ago
- ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino☆60Updated 4 months ago