nbulsi / also
A logic synthesis tool
☆73Updated last month
Alternatives and similar repositories for also:
Users that are interested in also are comparing it to the libraries listed below
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆26Updated last week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆46Updated 3 months ago
- EPFL logic synthesis benchmarks☆187Updated 8 months ago
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- Research paper based on or related to ABC.☆36Updated this week
- IDEA project source files☆106Updated 6 months ago
- GPU-based logic synthesis tool☆81Updated 9 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆133Updated 2 years ago
- DATC RDF☆50Updated 4 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆102Updated last year
- Showcase examples for EPFL logic synthesis libraries☆194Updated last year
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆140Updated last week
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated last week
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 4 months ago
- Rsyn – An Extensible Physical Synthesis Framework☆125Updated 9 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆46Updated 7 months ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- ☆22Updated 10 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆157Updated 4 months ago
- C++ logic network library☆229Updated this week
- UCSD Detailed Router☆85Updated 4 years ago
- Delay Calculation ToolKit☆31Updated 2 years ago
- DATC Robust Design Flow.☆37Updated 5 years ago
- for post graduates☆9Updated 3 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆15Updated 2 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆121Updated 4 months ago
- The first version of TritonPart☆26Updated last year
- A parallel global router using the Galois framework☆27Updated last year