nbulsi / also

Related projects: ⓘ

• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆17Updated 3 weeks ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆93Updated 2 weeks ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆159Updated 3 weeks ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆29Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆65Updated 2 months ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆176Updated 5 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆96Updated 6 months ago
• lsils / mockturtle
  C++ logic network library
  ☆204Updated this week
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆22Updated 4 years ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆16Updated 2 years ago
• zshi0616 / python-deepgate
  ☆18Updated 2 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆27Updated 3 weeks ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• asyncvlsi / SPRoute
  A parallel global router using the Galois framework
  ☆25Updated last year
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆120Updated last month
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆72Updated this week
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆118Updated last year
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 6 years ago
• lsils / percy
  C++ header-only exact synthesis library
  ☆15Updated last year
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆17Updated 11 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆14Updated this week
• geochrist / dctk
  Delay Calculation ToolKit
  ☆26Updated 2 years ago
• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆87Updated 4 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆17Updated 11 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆50Updated 4 years ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆53Updated 3 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆107Updated 3 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆79Updated 2 years ago
• zshi0616 / DeepGate2
  ☆24Updated 9 months ago