Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
☆16Dec 3, 2021Updated 4 years ago
Alternatives and similar repositories for iscas89_hl_verilog
Users that are interested in iscas89_hl_verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆71Jan 13, 2025Updated last year
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆23May 24, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- EPFL logic synthesis benchmarks☆234Mar 3, 2026Updated 3 weeks ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- Pipelined RISC-V CPU☆27Jun 9, 2021Updated 4 years ago
- Collection of digital hardware modules & projects (benchmarks)☆87Feb 27, 2026Updated last month
- ☆19Dec 21, 2020Updated 5 years ago
- ☆28Jun 25, 2024Updated last year
- download from opencores.org☆15May 4, 2018Updated 7 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- ☆14Feb 3, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- ☆10Dec 12, 2023Updated 2 years ago
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 9 years ago
- ☆14Jun 12, 2024Updated last year
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆15Sep 3, 2025Updated 6 months ago
- The top repository for the code accompanying our paper "Mind the Gap: Studying the Insecurity of Provably Secure Embedded Trusted Executi…☆16Aug 3, 2022Updated 3 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆41Aug 15, 2025Updated 7 months ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- reference block design for the ASAP7nm library in Cadence Innovus☆60Jun 25, 2024Updated last year
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/C…☆16Dec 3, 2025Updated 3 months ago
- This is a probabilistic SAT attack tool.☆13Jun 5, 2021Updated 4 years ago
- Equivalence checking with Yosys☆58Mar 19, 2026Updated last week
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆16Oct 4, 2022Updated 3 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆15Jul 6, 2025Updated 8 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Official implementation of paper "BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement".☆28Dec 19, 2025Updated 3 months ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- ☆21Sep 15, 2024Updated last year
- SMT Attack☆23Mar 5, 2021Updated 5 years ago
- An automatic clock gating utility☆52Apr 15, 2025Updated 11 months ago
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- A Python parser for hSpice output files and documentation of the hSpice output file format☆24Updated this week