Alternatives and similar repositories for iscas89_hl_verilog

Users that are interested in iscas89_hl_verilog are comparing it to the libraries listed below

• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆56Updated 8 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆34Updated 2 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆61Updated last week
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆51Updated last year
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated last month
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆94Updated 2 months ago
• zshi0616 / python-deepgate
  ☆23Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆84Updated 4 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆211Updated 2 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆42Updated last year
• cad-polito-it / I99T
  ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
  ☆60Updated 4 months ago
• nbulsi / also
  A logic synthesis tool
  ☆81Updated last week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated last month
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆15Updated 7 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 5 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆54Updated 3 months ago
• The-OpenROAD-Project / asap7
  ☆187Updated 6 months ago
• parallaxsw / OpenSTA
  ☆86Updated this week
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 2 months ago
• hsluoyz / Atalanta
  Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
  ☆83Updated last year
• ECASLab / AxLS
  AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis
  ☆12Updated this week
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆129Updated last year
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆155Updated 4 months ago
• vaughnbetz / COFFE
  ☆44Updated last year
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆36Updated last month
• Ravenslofty / librecell
  ☆25Updated 4 years ago
• LQY404 / EDA-info
  the awesome work, project and lab of EDA (Electronic Design Automation). continue update...
  ☆24Updated last year
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆37Updated last year