Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
☆16Dec 3, 2021Updated 4 years ago
Alternatives and similar repositories for iscas89_hl_verilog
Users that are interested in iscas89_hl_verilog are comparing it to the libraries listed below
Sorting:
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- Benchmarks for Yosys development☆24Feb 17, 2020Updated 6 years ago
- ☆19Dec 21, 2020Updated 5 years ago
- EPFL logic synthesis benchmarks☆231Nov 18, 2025Updated 3 months ago
- ☆27Jun 25, 2024Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆85Feb 27, 2026Updated last week
- Pipelined RISC-V CPU☆26Jun 9, 2021Updated 4 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Aug 15, 2025Updated 6 months ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆41Dec 24, 2025Updated 2 months ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- SIMPLER MAGIC: Synthesis and In-memory MaPping of Logic Execution in a single Row for Memristor Aided loGIC☆12Dec 5, 2019Updated 6 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆14Jul 31, 2024Updated last year
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆15Sep 28, 2017Updated 8 years ago
- AVR CPU Core Implementation in Verilog HDL.☆14Oct 28, 2018Updated 7 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- 一个通用的后台管理系统(Java)☆10Feb 6, 2025Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12May 29, 2021Updated 4 years ago
- ☆14Feb 3, 2025Updated last year
- ☆10Dec 12, 2023Updated 2 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- VGA LCD Core (OpenCores)☆14May 22, 2018Updated 7 years ago
- ☆14Jun 12, 2024Updated last year
- Equivalence checking with Yosys☆58Updated this week
- reference block design for the ASAP7nm library in Cadence Innovus☆59Jun 25, 2024Updated last year
- An automatic clock gating utility☆52Apr 15, 2025Updated 10 months ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆23May 24, 2025Updated 9 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 3 years ago
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆13Sep 14, 2025Updated 5 months ago
- Github repository of the AIStats 2024 paper: DE-HNN: An effective neural model for Circuit Netlist representation☆14Sep 3, 2025Updated 6 months ago
- Plugin manager using Qt framework to create Qt application based on custom loadable plugins☆12Oct 12, 2023Updated 2 years ago
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 4 years ago
- 集成 MudCore 框架的侠客行一百源码,使用fluffos v2019驱动☆13Jan 25, 2022Updated 4 years ago