bluesceada / iscas89_hl_verilog
Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")
☆13Updated 3 years ago
Alternatives and similar repositories for iscas89_hl_verilog:
Users that are interested in iscas89_hl_verilog are comparing it to the libraries listed below
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆43Updated last month
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆22Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆41Updated 3 months ago
- ☆22Updated 7 months ago
- Incremental Timing-Driven Placement, problem C of ICCAD contest 2015☆13Updated 7 years ago
- Research paper based on or related to ABC.☆25Updated this week
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated last month
- GPU-based logic synthesis tool☆80Updated 7 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆98Updated 11 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆82Updated last year
- ☆17Updated last year
- DATC RDF☆49Updated 4 years ago
- ☆69Updated 2 months ago
- A logic synthesis tool☆72Updated 2 years ago
- ☆28Updated last year
- IDEA project source files☆102Updated 3 months ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆91Updated 2 years ago
- EDA physical synthesis optimization kit☆50Updated last year
- DATC Robust Design Flow.☆37Updated 5 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆12Updated 2 years ago
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆9Updated this week
- Artificial Netlist Generator☆35Updated 11 months ago
- Material for OpenROAD Tutorial at DAC 2020☆46Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated last month
- ☆37Updated 10 months ago
- EPFL logic synthesis benchmarks☆174Updated 5 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆36Updated 7 months ago
- ☆24Updated last year
- ☆38Updated 2 years ago