Gy-Hu / E-SynLinks
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
☆41Updated last year
Alternatives and similar repositories for E-Syn
Users that are interested in E-Syn are comparing it to the libraries listed below
Sorting:
- ☆19Updated 5 years ago
- Research paper based on or related to ABC.☆65Updated 2 months ago
- ☆12Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 9 months ago
- A high-efficiency hybrid solving CEC algorithm☆14Updated 2 years ago
- Using e-graphs for logic synthesis☆30Updated this week
- ☆32Updated last month
- Collection for submission (Hardware Model Checking Benchmark)☆13Updated 2 months ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆37Updated 7 months ago
- GPU-based logic synthesis tool☆97Updated last month
- ☆44Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆34Updated last year
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 3 weeks ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆47Updated last year
- An advanced circuit-based sat solver☆36Updated 10 months ago
- This is a repo to store circuit design datasets☆19Updated last year
- This is a python repo for flattening Verilog☆20Updated 3 weeks ago
- ☆31Updated 2 years ago
- AIGER And-Inverter-Graph Library☆94Updated last week
- ☆27Updated last year
- Fast Symbolic Repair of Hardware Design Code☆32Updated 11 months ago
- Random Generator of Btor2 Files☆10Updated 2 years ago
- A logic synthesis tool☆84Updated 4 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆31Updated 9 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆34Updated 9 months ago