Gy-Hu / E-SynLinks
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
☆33Updated 11 months ago
Alternatives and similar repositories for E-Syn
Users that are interested in E-Syn are comparing it to the libraries listed below
Sorting:
- Research paper based on or related to ABC.☆46Updated this week
- ☆12Updated 2 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆19Updated 3 months ago
- ☆16Updated 4 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 8 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆23Updated 3 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 6 months ago
- A high-efficiency hybrid solving CEC algorithm☆12Updated 2 years ago
- AIGER And-Inverter-Graph Library☆83Updated last month
- Logic optimization and technology mapping tool.☆19Updated last year
- ☆22Updated last month
- AMulet 2. - A better AIG Multiplier Examination Tool☆25Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆34Updated 8 months ago
- ☆34Updated last year
- GPU-based logic synthesis tool☆83Updated 2 weeks ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆22Updated 2 years ago
- Random Generator of Btor2 Files☆10Updated last year
- Hardware Formal Verification Tool☆57Updated this week
- ☆18Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆30Updated last month
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆15Updated 2 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆30Updated 10 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated 9 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆17Updated 3 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 6 months ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated last month
- ☆10Updated 5 years ago
- BTOR2 MLIR project☆26Updated last year
- CoreIR Symbolic Analyzer☆73Updated 4 years ago