A high-efficiency hybrid solving CEC algorithm
☆14May 25, 2023Updated 3 years ago
Alternatives and similar repositories for Hybrid-CEC
Users that are interested in Hybrid-CEC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- SATZilla SAT feature extraction tool☆15Mar 23, 2026Updated 4 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated 2 years ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A generic parser and tool package for the BTOR2 format.☆49Sep 18, 2025Updated 10 months ago
- AIGER And-Inverter-Graph Library☆105Feb 17, 2026Updated 5 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- A Simple CDCL Solver☆37Mar 8, 2023Updated 3 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆30Jun 23, 2025Updated last year
- ☆30Jun 25, 2024Updated 2 years ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆32Dec 23, 2025Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- LLM-Assisted Hardware Formal Verification Tool☆113Jul 13, 2026Updated last month
- Collection of digital hardware modules & projects (benchmarks)☆107Feb 27, 2026Updated 5 months ago
- Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)☆26Dec 6, 2022Updated 3 years ago
- 面向 AI 编程 Agent 的开源形式验证技能库，聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV,…☆27Jul 27, 2026Updated 2 weeks ago
- ☆37Dec 2, 2023Updated 2 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆13Dec 31, 2024Updated last year
- A framework to ease parallelization of sequential SAT solvers☆36May 17, 2026Updated 2 months ago
- ☆15Sep 14, 2020Updated 5 years ago
- C++ Implementation of reduced order binary decision diagram data structure☆13Nov 11, 2015Updated 10 years ago
- EPFL logic synthesis benchmarks☆262Updated this week
- Yosys RTLIL dialect for MLIR☆24Jun 12, 2025Updated last year
- Cube-and-Conquer SAT solver☆44Jul 14, 2025Updated last year
- Pono: A flexible and extensible SMT-based model checker☆130Updated this week
- Implementation of local search-based algorithms for solving SAT and Max-SAT in Python☆13Dec 6, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆19Dec 21, 2020Updated 5 years ago
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆23Jan 28, 2026Updated 6 months ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆28Jun 9, 2025Updated last year
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 8 months ago
- Recent papers related to hardware formal verification.☆78Sep 20, 2023Updated 2 years ago
- ☆30Jan 30, 2025Updated last year
- A logic synthesis tool☆90Aug 8, 2026Updated last week