A high-efficiency hybrid solving CEC algorithm
☆14May 25, 2023Updated 3 years ago
Alternatives and similar repositories for Hybrid-CEC
Users that are interested in Hybrid-CEC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An advanced circuit-based sat solver☆38Feb 24, 2025Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated last year
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 3 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆29Jun 23, 2025Updated last year
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A generic parser and tool package for the BTOR2 format.☆48Sep 18, 2025Updated 9 months ago
- LLM-Assisted Hardware Formal Verification Tool☆110Jun 28, 2026Updated last week
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- AIGER And-Inverter-Graph Library☆103Feb 17, 2026Updated 4 months ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆30Dec 23, 2025Updated 6 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- SATZilla SAT feature extraction tool☆14Mar 23, 2026Updated 3 months ago
- C++ implementation of FRAIGs. Won the 1st place in 2018 Cadence-sponsored contest in NTU DSnP.☆10Oct 21, 2020Updated 5 years ago
- A Simple CDCL Solver☆36Mar 8, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A framework to ease parallelization of sequential SAT solvers☆36May 17, 2026Updated last month
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆26May 24, 2025Updated last year
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- ☆29Jun 25, 2024Updated 2 years ago
- Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)☆25Dec 6, 2022Updated 3 years ago
- C++ Implementation of reduced order binary decision diagram data structure☆13Nov 11, 2015Updated 10 years ago
- ☆15Sep 14, 2020Updated 5 years ago
- EPFL logic synthesis benchmarks