Yu-Maryland / MapTuneLinks
MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunxi Yu IEEE/ACM International Conference On Computer Aided Design (ICCAD'24)
☆22Updated 10 months ago
Alternatives and similar repositories for MapTune
Users that are interested in MapTune are comparing it to the libraries listed below
Sorting:
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Updated last year
- Research paper based on or related to ABC.☆70Updated 3 weeks ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- Problems and Results of IWLS 2022 Programming Contest☆21Updated 9 months ago
- ☆19Updated 5 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆56Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆80Updated 2 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- Awesome machine learning for logic synthesis☆30Updated 3 years ago
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- ☆27Updated last year
- GPU-based logic synthesis tool☆97Updated 2 months ago
- A logic synthesis tool☆84Updated 5 months ago
- Cell Layout Generation for DTCO/STCO Exploration Toolkit☆22Updated 8 months ago
- A high-efficiency hybrid solving CEC algorithm☆14Updated 2 years ago
- ☆13Updated 3 years ago
- Using e-graphs for logic synthesis (ICCAD'25)☆32Updated this week
- ☆20Updated 3 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated last month
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Updated 6 years ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆18Updated 3 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆61Updated last year
- EPFL logic synthesis benchmarks☆227Updated 2 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Updated last year
- ☆31Updated 2 years ago
- ☆30Updated last year
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆21Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆35Updated 10 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Updated 9 months ago