Alternatives and similar repositories for MapTune:

Users that are interested in MapTune are comparing it to the libraries listed below

• amahzoon / genmul
  ☆16Updated 4 years ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆28Updated 2 weeks ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆27Updated 7 months ago
• Entropy-xcy / sns
  ☆15Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 2 months ago
• lnis-uofu / ML-Mapper
  ☆11Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆46Updated 3 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 2 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆17Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 10 months ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• zshi0616 / python-deepgate
  ☆22Updated 8 months ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆21Updated last year
• zshi0616 / DeepGate2
  ☆28Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆42Updated 5 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆43Updated 2 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 7 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆25Updated this week
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 6 months ago
• cure-lab / DeepGate2
  ☆14Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆26Updated 5 years ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆23Updated 4 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆25Updated 2 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆28Updated 9 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆12Updated 8 months ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆21Updated 2 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• ycunxi / FLowGen-CNNs-DAC18
  ☆14Updated 6 years ago