Alternatives and similar repositories for elve

Users that are interested in elve are comparing it to the libraries listed below

• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆29Updated 3 years ago
• lsils / kitty
  C++ truth table library
  ☆62Updated 4 months ago
• ymanerka / rtlcheck
  RTLCheck
  ☆23Updated 7 years ago
• pulp-platform / ELAU
  ☆20Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 7 months ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆41Updated 2 weeks ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 6 months ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆37Updated last year
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆16Updated 5 years ago
• chengyinwu / V3
  An Extensible Framework for Hardware Verification and Debugging
  ☆18Updated 3 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆22Updated 5 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆24Updated 3 years ago
• JKomp / AIGER
  Python version of tools to work with AIG formatted files
  ☆12Updated 6 months ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆42Updated 3 months ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 5 months ago
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 6 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 4 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 8 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆15Updated 8 years ago
• UCSBarchlab / owl
  Control Logic Synthesis: Drawing the Rest of the OWL
  ☆13Updated last year
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 4 months ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 7 years ago
• amahzoon / genmul
  ☆18Updated 4 years ago