Alternatives and similar repositories for elve

Users that are interested in elve are comparing it to the libraries listed below

• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• pulp-platform / ELAU
  ☆19Updated last year
• foshardware / lsc
  Libre Silicon Compiler
  ☆22Updated 4 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆40Updated this week
• ymanerka / rtlcheck
  RTLCheck
  ☆22Updated 6 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• leonardt / hwtypes
  Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics
  ☆18Updated last year
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated last month
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated 4 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• chengyinwu / QuteRTL
  QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification
  ☆16Updated 8 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 4 months ago
• lsils / kitty
  C++ truth table library
  ☆59Updated last month
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• EDAPack / edapack
  Provides a packaged collection of open source EDA tools
  ☆12Updated 6 years ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆43Updated last week
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 2 months ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• mgudemann / iimc
  ☆14Updated 7 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆23Updated 3 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated last month
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆21Updated 5 years ago