stdgregwar / elveLinks
ELVE : ELVE Logic Visualization Engine
☆11Updated 8 years ago
Alternatives and similar repositories for elve
Users that are interested in elve are comparing it to the libraries listed below
Sorting:
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Updated 3 years ago
- An advanced header-only exact synthesis library☆29Updated 2 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Updated 4 years ago
- ☆20Updated last year
- RTLCheck☆22Updated 7 years ago
- design and verification of asynchronous circuits☆41Updated last month
- The PE for the second generation CGRA (garnet).☆17Updated 6 months ago
- PipeProof☆11Updated 5 years ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 5 years ago
- Collection of test cases for Yosys☆17Updated 3 years ago
- BTOR2 MLIR project☆26Updated last year
- Logic circuit analysis and optimization☆42Updated 2 months ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- Niklas Een's ABC/ZZ framework☆24Updated 3 years ago
- Arithmetic multiplier benchmarks☆11Updated 7 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 4 months ago
- Using e-graphs to synthesize netlists from boolean logic.☆14Updated 2 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 5 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- ☆19Updated last year
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Updated 9 years ago
- Libre Silicon Compiler☆22Updated 4 years ago
- ☆14Updated 7 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆14Updated 8 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- Optimization results for superconducting electronic (SCE) circuits☆15Updated last year
- Hardware generator debugger☆76Updated last year
- IRSIM switch-level simulator for digital circuits☆34Updated 7 months ago
- ☆19Updated 10 years ago
- Hardware Formal Verification☆16Updated 5 years ago