Alternatives and similar repositories for elve

Users that are interested in elve are comparing it to the libraries listed below

• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 2 weeks ago
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 5 years ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆31Updated 3 years ago
• lsils / kitty
  C++ truth table library
  ☆64Updated 6 months ago
• pulp-platform / ELAU
  ☆20Updated last year
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆15Updated 9 years ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• ymanerka / rtlcheck
  RTLCheck
  ☆24Updated 7 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• Coloquinte / quaigh
  Logic circuit analysis and optimization
  ☆44Updated 5 months ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆18Updated 9 months ago
• mgudemann / iimc
  ☆14Updated 8 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 7 months ago
• snishizawa / asap7_snps
  Supplemental technology files for ASAP7 PDK with Synopsys design flow
  ☆22Updated 3 years ago
• comsec-group / cellift-yosys
  A fork of Yosys that integrates the CellIFT pass
  ☆13Updated 6 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆46Updated 4 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• berkeley-abc / abc-zz
  Niklas Een's ABC/ZZ framework
  ☆24Updated 3 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆38Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 4 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 2 weeks ago
• tdb-alcorn / chisel-formal
  ☆24Updated 4 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆18Updated 5 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆12Updated 8 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆15Updated 4 years ago
• The-OpenROAD-Project / Birds-of-a-Feather-Open-Source-Academic-EDA-Software
  Welcome to Birds-of-a-Feather: Open-Source-Academic-EDA-Software !
  ☆14Updated 6 years ago