Alternatives and similar repositories for ML-Mapper

Users that are interested in ML-Mapper are comparing it to the libraries listed below

• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 5 months ago
• cure-lab / DeepGate2
  ☆15Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 8 months ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• krzhu / abc_py
  Simple Python interface for ABC
  ☆23Updated 2 years ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆61Updated this week
• zshi0616 / DeepGate2
  ☆29Updated last year
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆23Updated 3 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated last month
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆63Updated 2 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆29Updated 2 years ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆130Updated last month
• lrakai / gate-sizing
  Optimal gate sizing of digital circuits using geometric programming
  ☆11Updated 9 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆36Updated last year
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆53Updated 2 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 8 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆54Updated 3 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆56Updated 8 months ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• zshi0616 / python-deepgate
  ☆23Updated last year
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆52Updated 2 months ago
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆18Updated 5 months ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆17Updated 2 years ago
• nbulsi / also
  A logic synthesis tool
  ☆80Updated last week
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆210Updated last month