Alternatives and similar repositories for CULS

Users that are interested in CULS are comparing it to the libraries listed below

• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 3 weeks ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆26Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated last month
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆122Updated last week
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated last month
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆48Updated 4 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆28Updated 3 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆57Updated last year
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• cuhk-eda / cu-gr-2
  ☆44Updated last year
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• NVlabs / Differentiable-Global-Router
  ☆18Updated 6 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆87Updated 4 years ago
• zshi0616 / python-deepgate
  ☆22Updated 11 months ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆44Updated 3 weeks ago
• IntelLabs / FloorSet
  ☆72Updated 5 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆48Updated last week
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆126Updated 10 months ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆31Updated 3 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆52Updated 10 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• cuhk-eda / GCS-Timer
  ☆20Updated 7 months ago