cuhk-eda / CULSLinks
GPU-based logic synthesis tool
☆97Updated 3 weeks ago
Alternatives and similar repositories for CULS
Users that are interested in CULS are comparing it to the libraries listed below
Sorting:
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆109Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆74Updated 3 weeks ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆89Updated 7 months ago
- The first version of TritonPart☆31Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆149Updated 6 months ago
- ☆26Updated last year
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆75Updated 6 months ago
- ☆41Updated 3 years ago
- ☆90Updated 6 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆141Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Updated this week
- ☆77Updated last week
- Rsyn – An Extensible Physical Synthesis Framework☆135Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated 11 months ago
- DATC RDF☆50Updated 5 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆59Updated 6 months ago
- A logic synthesis tool☆83Updated 3 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆59Updated 11 months ago
- ☆35Updated 5 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆166Updated 8 months ago
- ☆29Updated last year
- ☆21Updated last year
- EPFL logic synthesis benchmarks☆223Updated last month
- IDEA project source files☆111Updated 2 months ago
- UCSD Detailed Router☆94Updated 4 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆189Updated 7 months ago
- ☆31Updated 2 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆140Updated 2 years ago