cuhk-eda / CULSLinks
GPU-based logic synthesis tool
☆86Updated last month
Alternatives and similar repositories for CULS
Users that are interested in CULS are comparing it to the libraries listed below
Sorting:
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆133Updated last month
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 2 months ago
- The first version of TritonPart☆28Updated last year
- ☆74Updated last month
- ☆39Updated 2 years ago
- Rsyn – An Extensible Physical Synthesis Framework☆126Updated last year
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆53Updated 6 months ago
- ☆22Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆31Updated 3 weeks ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 6 months ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆137Updated 2 years ago
- A logic synthesis tool☆77Updated 3 weeks ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆47Updated last month
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆70Updated 2 months ago
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆41Updated last month
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 3 months ago
- ☆24Updated last year
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆174Updated 2 months ago
- EPFL logic synthesis benchmarks☆203Updated 2 weeks ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆21Updated 3 months ago
- DATC RDF☆50Updated 5 years ago
- ☆31Updated 4 years ago
- ☆81Updated last month
- IDEA project source files☆107Updated 8 months ago
- Research paper based on or related to ABC.☆49Updated 3 weeks ago
- ☆28Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆135Updated 2 years ago