cuhk-eda / CULS

Related projects ⓘ

Alternatives and complementary repositories for CULS

• cuhk-eda / Xplace
  Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
  ☆99Updated 4 months ago
• ABKGroup / TritonRoute-WXL
  ☆25Updated 4 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆35Updated 2 months ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆36Updated last month
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆97Updated 8 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆26Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆47Updated 2 weeks ago
• Yu-Maryland / Verilog-to-PyG
  ☆20Updated 6 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆22Updated 10 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆17Updated 4 months ago
• ABKGroup / PROBE_SMT_AutoCell
  ☆17Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆75Updated 3 weeks ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆48Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• zshi0616 / python-deepgate
  ☆21Updated 4 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆20Updated this week
• alanminko / iwls2022-ls-contest
  Problems and Results of IWLS 2022 Programming Contest
  ☆16Updated 2 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆36Updated last year
• zshi0616 / DeepGate2
  ☆27Updated 11 months ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆15Updated last week
• cuhk-eda / GCS-Timer
  ☆17Updated last month
• IntelLabs / FloorSet
  ☆50Updated 3 weeks ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆33Updated last week
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆33Updated 8 months ago
• TILOS-AI-Institute / HypergraphPartitioning
  Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes
  ☆58Updated 3 weeks ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆122Updated 4 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• cuhk-eda / cu-gr-2
  ☆35Updated 10 months ago
• UTDA-group / BoxRouter
  BoxRouter2.0 is a new global router for ultimate routability. It is inspired by BoxRouter [1], but can perform multi-layer routing with 2…
  ☆20Updated 5 years ago