Alternatives and similar repositories for CULS

Users that are interested in CULS are comparing it to the libraries listed below

• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆58Updated last week
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated 2 weeks ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆104Updated last year
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆26Updated last year
• cuhk-eda / Xplace
  Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization
  ☆120Updated last week
• tsung-wei-huang / ece5960-physical-design
  ☆38Updated 2 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• cuhk-eda / GCS-Timer
  ☆20Updated 7 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆81Updated 2 weeks ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆47Updated 4 months ago
• cuhk-eda / ripple
  Pin-Accessible Legalization for Mixed-Cell-Height Circuits
  ☆28Updated 3 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• zshi0616 / python-deepgate
  ☆22Updated 10 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆40Updated this week
• nbulsi / also
  A logic synthesis tool
  ☆73Updated last month
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• ABKGroup / PROBE_SMT_AutoCell
  ☆18Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆48Updated 7 months ago
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆87Updated 4 years ago
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆40Updated last week
• ABKGroup / TritonRoute-WXL
  ☆30Updated 4 years ago
• cuhk-eda / cu-gr
  CUGR, VLSI Global Routing Tool Developed by CUHK
  ☆135Updated 2 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• IntelLabs / FloorSet
  ☆71Updated 5 months ago
• NVlabs / Differentiable-Global-Router
  ☆18Updated 5 months ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆125Updated 9 months ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆73Updated 7 years ago