Alternatives and similar repositories for abc

Users that are interested in abc are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆531Updated 2 weeks ago
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,177Updated last week
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆223Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆481Updated last week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆899Updated this week
• lsils / mockturtle
  C++ logic network library
  ☆268Updated 2 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆681Updated 3 weeks ago
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆680Updated this week
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆201Updated last year
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆759Updated last year
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,711Updated last week
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆351Updated last week
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆534Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆729Updated last month
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆620Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆627Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆686Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆472Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆678Updated this week
• gtkwave / gtkwave
  GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard …
  ☆878Updated this week
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆975Updated 2 months ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆749Updated last month
• nbulsi / also
  A logic synthesis tool
  ☆83Updated 3 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆531Updated last year
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆548Updated 2 months ago
• Nic30 / hdlConvertor
  Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
  ☆310Updated 5 months ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆230Updated this week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆458Updated last month
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,186Updated this week