Alternatives and similar repositories for abc

Users that are interested in abc are comparing it to the libraries listed below

• The-OpenROAD-Project / OpenSTA
  OpenSTA engine
  ☆539Updated last month
• verilog-to-routing / vtr-verilog-to-routing
  Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆1,183Updated last week
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆224Updated last month
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆485Updated this week
• MikePopoloski / slang
  SystemVerilog compiler and language services
  ☆915Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆693Updated last month
• OpenTimer / OpenTimer
  A High-performance Timing Analysis Tool for VLSI Systems
  ☆683Updated 2 weeks ago
• lsils / mockturtle
  C++ logic network library
  ☆272Updated 3 months ago
• The-OpenROAD-Project / OpenROAD-flow-scripts
  OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
  ☆544Updated this week
• PyHDI / Pyverilog
  Python-based Hardware Design Processing Toolkit for Verilog HDL
  ☆764Updated last year
• SymbioticEDA / riscv-formal
  RISC-V Formal Verification Framework
  ☆621Updated 3 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆201Updated last year
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆354Updated this week
• chipsalliance / verible
  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
  ☆1,737Updated 2 weeks ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆432Updated 4 months ago
• VLSIDA / OpenRAM
  An open-source static random access memory (SRAM) compiler.
  ☆985Updated 2 months ago
• limbo018 / DREAMPlace
  Deep learning toolkit-enabled VLSI placement
  ☆922Updated 2 weeks ago
• black-parrot / black-parrot
  A Linux-capable RISC-V multicore for and by the world
  ☆754Updated 2 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆737Updated 3 weeks ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆749Updated last year
• RTimothyEdwards / magic
  Magic VLSI Layout Tool
  ☆599Updated this week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆754Updated 3 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆632Updated 2 weeks ago
• pymtl / pymtl3
  Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
  ☆439Updated 4 months ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,236Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆557Updated 2 months ago
• nbulsi / also
  A logic synthesis tool
  ☆84Updated 4 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated 2 months ago
• YosysHQ / yosys
  Yosys Open SYnthesis Suite
  ☆4,220Updated this week
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 3 weeks ago