lsils / SCE-benchmarksLinks
Optimization results for superconducting electronic (SCE) circuits
☆15Updated last year
Alternatives and similar repositories for SCE-benchmarks
Users that are interested in SCE-benchmarks are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆65Updated last week
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- A logic synthesis tool☆82Updated last month
- GPU-based logic synthesis tool☆92Updated 2 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆57Updated 9 months ago
- IDEA project source files☆108Updated 2 weeks ago
- C++ header-only exact synthesis library☆18Updated 2 years ago
- ☆77Updated 4 months ago
- ☆13Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆53Updated 9 months ago
- ABACUS is a tool for approximate logic synthesis☆14Updated 5 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 6 months ago
- ☆27Updated last year
- DATC RDF☆50Updated 5 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- ☆18Updated 4 years ago
- ☆88Updated 4 months ago
- ☆23Updated 11 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- This is a python repo for flattening Verilog☆20Updated 5 months ago
- A LEF/DEF Utility.☆32Updated 6 years ago
- EDA physical synthesis optimization kit☆62Updated last year
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- Showcase examples for EPFL logic synthesis libraries☆198Updated last year
- An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization☆31Updated last year
- ☆106Updated 5 years ago
- The first version of TritonPart☆29Updated last year
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆34Updated 3 months ago