Yu-Maryland / GamoraLinks
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
☆55Updated 11 months ago
Alternatives and similar repositories for Gamora
Users that are interested in Gamora are comparing it to the libraries listed below
Sorting:
- ☆29Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆34Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆59Updated 6 months ago
- Collection of digital hardware modules & projects (benchmarks)☆74Updated 2 weeks ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆53Updated last year
- ☆31Updated 2 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆25Updated 3 years ago
- ☆20Updated 3 years ago
- ☆42Updated last year
- GPU-based logic synthesis tool☆97Updated 3 weeks ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆19Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 8 months ago
- ☆26Updated last year
- ☆16Updated 2 years ago
- ☆18Updated 4 years ago
- ☆54Updated 6 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆40Updated last year
- ☆16Updated 3 years ago
- Hypergraph Partitioning: benchmarks, evaluators, best known solutions and codes☆76Updated 3 weeks ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆23Updated last year
- This is a python repo for flattening Verilog☆20Updated 7 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆30Updated 8 months ago
- Dataset for ML-guided Accelerator Design☆42Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆44Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- Using e-graphs for logic synthesis☆28Updated this week
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆37Updated 6 months ago
- ☆41Updated 3 years ago