Alternatives and similar repositories for percy

Users that are interested in percy are comparing it to the libraries listed below

• msoeken / cirkit
  A circuit toolkit
  ☆106Updated 5 years ago
• hriener / lorina
  C++ parsing library for simple formats used in logic synthesis and formal verification
  ☆38Updated last year
• lsils / percy
  C++ header-only exact synthesis library
  ☆18Updated 2 years ago
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆201Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• amahzoon / genmul
  ☆18Updated 5 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆94Updated 4 months ago
• lsils / kitty
  C++ truth table library
  ☆63Updated 5 months ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆17Updated 3 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 7 months ago
• lsils / mockturtle
  C++ logic network library
  ☆272Updated 3 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆32Updated 4 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 3 years ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• nbulsi / also
  A logic synthesis tool
  ☆83Updated 3 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆111Updated 2 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆45Updated 3 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆64Updated last month
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• lsils / bill
  C++ header-only reasoning library
  ☆17Updated last year
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• lsils / SCE-benchmarks
  Optimization results for superconducting electronic (SCE) circuits
  ☆17Updated 2 years ago
• temelmertcan / multgen
  Integer Multiplier Generator for Verilog
  ☆23Updated 5 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆100Updated this week
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 5 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆19Updated 3 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year