arminbiere / aiger
AIGER And-Inverter-Graph Library
☆67Updated this week
Alternatives and similar repositories for aiger:
Users that are interested in aiger are comparing it to the libraries listed below
- Reads a state transition system and performs property checking☆76Updated 3 months ago
- CoreIR Symbolic Analyzer☆63Updated 4 years ago
- A logic synthesis tool☆72Updated 2 years ago
- Hardware Model Checker☆32Updated this week
- A generic parser and tool package for the BTOR2 format.☆41Updated 2 months ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆65Updated this week
- EPFL logic synthesis benchmarks☆175Updated 5 months ago
- C++ logic network library☆221Updated 4 months ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆13Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆43Updated last month
- Research paper based on or related to ABC.☆25Updated this week
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆27Updated 7 months ago
- Problems and Results of IWLS 2022 Programming Contest☆17Updated 2 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆23Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆22Updated last month
- C++ header-only exact synthesis library☆15Updated 2 years ago
- Recent papers related to hardware formal verification.☆64Updated last year
- Pono: A flexible and extensible SMT-based model checker☆90Updated last week
- ☆12Updated 2 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆14Updated 8 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆17Updated 4 months ago
- A Formal Verification Framework for Chisel☆18Updated 10 months ago
- ☆15Updated 4 years ago
- An advanced header-only exact synthesis library☆24Updated 2 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆75Updated 7 months ago
- high-performance RTL simulator☆152Updated 8 months ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆35Updated 7 months ago
- IDEA project source files☆102Updated 3 months ago
- Showcase examples for EPFL logic synthesis libraries☆192Updated 10 months ago