Alternatives and similar repositories for aiger

Users that are interested in aiger are comparing it to the libraries listed below

• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆51Updated last month
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆85Updated 5 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 3 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• shaowei-cai-group / X-SAT
  An advanced circuit-based sat solver
  ☆29Updated 6 months ago
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆13Updated 2 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆62Updated last week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆73Updated 4 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆81Updated this week
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆21Updated 4 months ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 10 months ago
• nbulsi / also
  A logic synthesis tool
  ☆78Updated last month
• lsils / mockturtle
  C++ logic network library
  ☆245Updated 2 weeks ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆15Updated 3 years ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆28Updated 4 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆77Updated last year
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆206Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆195Updated last year
• SPbSAT / cirbo
  ☆22Updated 2 months ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆72Updated last year
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 8 months ago
• whaaswijk / percy
  An advanced header-only exact synthesis library
  ☆27Updated 2 years ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 2 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago