lsils / mockturtle
C++ logic network library
☆221Updated 3 months ago
Alternatives and similar repositories for mockturtle:
Users that are interested in mockturtle are comparing it to the libraries listed below
- Showcase examples for EPFL logic synthesis libraries☆192Updated 10 months ago
- EPFL logic synthesis benchmarks☆174Updated 5 months ago
- IDEA project source files☆102Updated 3 months ago
- A logic synthesis tool☆72Updated 2 years ago
- A circuit toolkit☆96Updated 4 years ago
- AIGER And-Inverter-Graph Library☆67Updated last month
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆21Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆98Updated 11 months ago
- GPU-based logic synthesis tool☆80Updated 7 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆150Updated last month
- UCSD Detailed Router☆84Updated 4 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆215Updated this week
- Rsyn – An Extensible Physical Synthesis Framework☆122Updated 6 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆135Updated 4 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆42Updated last month
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆56Updated 8 months ago
- RePlAce global placement tool☆223Updated 4 years ago
- ☆102Updated 5 years ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆89Updated 5 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆128Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated last month
- ☆38Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆40Updated 3 months ago
- C++ header-only exact synthesis library☆15Updated 2 years ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆112Updated last month
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆132Updated last year
- C++ parsing library for simple formats used in logic synthesis and formal verification☆35Updated 7 months ago
- Problems and Results of IWLS 2022 Programming Contest☆17Updated 2 years ago
- high-performance RTL simulator☆151Updated 7 months ago
- Database and Tool Framework for EDA☆110Updated 4 years ago