lnis-uofu / LSOracleLinks
IDEA project source files
☆107Updated 8 months ago
Alternatives and similar repositories for LSOracle
Users that are interested in LSOracle are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- DATC RDF☆50Updated 5 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- ☆78Updated last week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆53Updated 6 months ago
- RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA☆90Updated 5 years ago
- ☆105Updated 5 years ago
- UCSD Detailed Router☆90Updated 4 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- A logic synthesis tool☆77Updated 3 weeks ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 8 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆27Updated 5 years ago
- EDA physical synthesis optimization kit☆60Updated last year
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆93Updated last month
- EPFL logic synthesis benchmarks☆200Updated 2 weeks ago
- C++ logic network library☆243Updated this week
- ☆74Updated last month
- Rsyn – An Extensible Physical Synthesis Framework☆126Updated last year
- A Standalone Structural Verilog Parser☆96Updated 3 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 3 months ago
- GPU-based logic synthesis tool☆83Updated last month
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆31Updated 3 weeks ago
- Showcase examples for EPFL logic synthesis libraries☆194Updated last year
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 4 years ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆174Updated 2 months ago
- ☆178Updated 4 months ago
- Introductory course into static timing analysis (STA).☆96Updated last month