Alternatives and similar repositories for LSOracle:

Users that are interested in LSOracle are comparing it to the libraries listed below

• cuhk-eda / ripple-fpga
  RippleFPGA, A Simultaneous Pack-and-Place Algorithm for UltraScale FPGA
  ☆90Updated 5 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆102Updated last year
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆57Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆55Updated this week
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• parallaxsw / OpenSTA
  ☆67Updated this week
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆47Updated 2 years ago
• RsynTeam / rsyn-x
  Rsyn – An Extensible Physical Synthesis Framework
  ☆125Updated 9 months ago
• pkuzjx / eda-collection
  ☆105Updated 5 years ago
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆45Updated 3 months ago
• PKU-IDEA / OpenPARF
  🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
  ☆140Updated last week
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆187Updated 8 months ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆26Updated last week
• The-OpenROAD-Project / TritonRoute
  UCSD Detailed Router
  ☆85Updated 4 years ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆81Updated this week
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆53Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆26Updated 5 years ago
• geochrist / dctk
  Delay Calculation ToolKit
  ☆31Updated 2 years ago
• nbulsi / also
  A logic synthesis tool
  ☆73Updated 3 weeks ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• limbo018 / Limbo
  Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
  ☆157Updated 4 months ago
• lsils / mockturtle
  C++ logic network library
  ☆229Updated this week
• PrincetonUniversity / OPDB
  OpenPiton Design Benchmark
  ☆25Updated 2 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆81Updated 9 months ago
• ABKGroup / PROBE3.0
  ☆43Updated last year
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆91Updated 3 years ago
• The-OpenROAD-Project / asap7
  ☆155Updated last month
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆72Updated 7 years ago
• YuanTingHsieh / ITDP
  Incremental Timing-Driven Placement, problem C of ICCAD contest 2015
  ☆13Updated 7 years ago