Alternatives and similar repositories for DeepGate2:

Users that are interested in DeepGate2 are comparing it to the libraries listed below

• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆21Updated last year
• Entropy-xcy / sns
  ☆15Updated 2 years ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 2 months ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆22Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆25Updated 2 years ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆43Updated 6 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆44Updated last week
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆16Updated 3 months ago
• lnis-uofu / ML-Mapper
  ☆11Updated 2 years ago
• krzhu / abc_py
  Simple Python interface for ABC
  ☆23Updated last year
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆41Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 6 months ago
• zshi0616 / python-deepgate
  ☆22Updated 8 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆22Updated 8 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 3 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 2 months ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆48Updated 9 months ago
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆16Updated 10 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆17Updated 5 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆49Updated 4 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆28Updated 10 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆11Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆24Updated 4 months ago