Alternatives and similar repositories for X-SAT

Users that are interested in X-SAT are comparing it to the libraries listed below

• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆13Updated 2 years ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• arminbiere / aiger
  AIGER And-Inverter-Graph Library
  ☆86Updated 3 weeks ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆35Updated last year
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆51Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆21Updated 4 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆28Updated 4 months ago
• nbulsi / also
  A logic synthesis tool
  ☆78Updated last month
• yaoxufeng / RTLRewriter-Bench
  ☆36Updated last year
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆62Updated last week
• achieve-lab / assertion_data_for_LLM
  ☆16Updated 6 months ago
• saleh1204 / sis
  Logic Synthesis System from UC Berkeley (Unofficial Distribution)
  ☆15Updated 6 years ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆72Updated last year
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆41Updated 3 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated 2 weeks ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 10 months ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆19Updated 8 months ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 10 months ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆23Updated 2 years ago
• fangwenji / tacas23-wasim
  ☆12Updated 2 years ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆85Updated 5 months ago
• SPbSAT / cirbo
  ☆22Updated 2 months ago