lirui-shanghaitech / CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
☆184Updated last year
Alternatives and similar repositories for CNN-Accelerator-VLSI:
Users that are interested in CNN-Accelerator-VLSI are comparing it to the libraries listed below
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- ☆104Updated 4 years ago
- IC implementation of Systolic Array for TPU☆207Updated 5 months ago
- Deep Learning Accelerator (Convolution Neural Networks)☆179Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆144Updated 9 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆172Updated last year
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆157Updated last year
- Convolutional Neural Network Using High Level Synthesis☆85Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- IC implementation of TPU☆112Updated 5 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆156Updated 4 months ago
- An AXI4 crossbar implementation in SystemVerilog☆138Updated last month
- Implementation of CNN using Verilog☆209Updated 7 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆28Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆49Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆54Updated last month
- A FPGA Based CNN accelerator, following Google's TPU V1.☆143Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- AXI总线连接器☆96Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆106Updated last month
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago