Convolutional accelerator kernel, target ASIC & FPGA
☆245Apr 10, 2023Updated 2 years ago
Alternatives and similar repositories for CNN-Accelerator-VLSI
Users that are interested in CNN-Accelerator-VLSI are comparing it to the libraries listed below
Sorting:
- ☆124Jul 22, 2020Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆66Aug 9, 2022Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆198Dec 15, 2017Updated 8 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- IC implementation of Systolic Array for TPU☆340Oct 21, 2024Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆166Mar 5, 2025Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆195Mar 20, 2024Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- Systolic-array based Deep Learning Accelerator generator☆28Dec 11, 2020Updated 5 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆136Jul 22, 2025Updated 7 months ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆224Oct 16, 2025Updated 4 months ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆172Jul 25, 2019Updated 6 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆578Feb 19, 2021Updated 5 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆128Jun 27, 2023Updated 2 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆218Dec 22, 2020Updated 5 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆385Dec 27, 2023Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆231Mar 24, 2024Updated last year
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆270Apr 1, 2024Updated last year
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Oct 2, 2019Updated 6 years ago
- eyeriss-chisel3☆40May 2, 2022Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆125Aug 27, 2024Updated last year
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 3 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆164Dec 13, 2020Updated 5 years ago
- RTL implementation of Flex-DPE.☆115Feb 22, 2020Updated 6 years ago
- Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximat…☆16Mar 3, 2023Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆44Sep 26, 2023Updated 2 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆26Apr 7, 2025Updated 11 months ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- An OpenCL-based FPGA Accelerator for Convolutional Neural Networks☆1,368Feb 14, 2022Updated 4 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Apr 4, 2022Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆151Feb 11, 2025Updated last year