XueTianyu24 / cnn_accelerator
【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
☆135Updated last year
Alternatives and similar repositories for cnn_accelerator:
Users that are interested in cnn_accelerator are comparing it to the libraries listed below
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆132Updated 2 months ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆69Updated 2 years ago
- ☆205Updated 9 months ago
- some interesting demos for starters☆68Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆42Updated 3 years ago
- FPGA project☆203Updated 2 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆73Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆163Updated 10 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆29Updated 2 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆76Updated 3 years ago
- FPGA☆144Updated 7 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆29Updated 3 weeks ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆194Updated last year
- 一个开源的FPGA神经网络加速器。☆139Updated last year
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆437Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆175Updated last year
- PYNQ学习资料☆160Updated 5 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆61Updated 6 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆141Updated 10 months ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆132Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆12Updated 8 months ago
- CNN accelerator implemented with Spinal HDL☆144Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆137Updated 7 months ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆289Updated last year
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- CPU Design Based on RISCV ISA☆84Updated 7 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆136Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆73Updated 3 years ago
- ☆59Updated 2 years ago