Starrynightzyq / soNN
A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
☆27Updated 3 years ago
Alternatives and similar repositories for soNN:
Users that are interested in soNN are comparing it to the libraries listed below
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- ☆24Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆40Updated 5 years ago
- CNN accelerator using NoC architecture☆15Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆27Updated 4 years ago
- HLS for Networks-on-Chip☆32Updated 3 years ago
- ☆26Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆26Updated 3 months ago
- Ratatoskr NoC Simulator☆22Updated 3 years ago
- ☆13Updated last year
- ☆25Updated 4 years ago
- ☆60Updated 6 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- Systolic-array based Deep Learning Accelerator generator☆25Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆42Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆11Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 7 years ago
- The Verilog source code for DRUM approximate multiplier.☆29Updated last year
- ☆12Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆13Updated 2 weeks ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆10Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆39Updated 4 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆67Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago