hardware design of universal NPU(CNN accelerator) for various convolution neural network
☆181Mar 5, 2025Updated last year
Alternatives and similar repositories for universal_NPU-CNN_accelerator
Users that are interested in universal_NPU-CNN_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆264Apr 10, 2023Updated 3 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆331Aug 16, 2018Updated 8 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆157Jul 22, 2025Updated last year
- Open-source Neural Processing Unit (NPU) from China ❤☆55Jan 29, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆15Apr 24, 2023Updated 3 years ago
- 第四届全国大学生嵌入式比赛SoC☆12Apr 1, 2022Updated 4 years ago
- ☆265Apr 8, 2024Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆79Aug 9, 2022Updated 4 years ago
- ☆28Jun 21, 2024Updated 2 years ago
- ☆12Sep 18, 2024Updated 2 years ago
- ☆128Jul 22, 2020Updated 6 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆36Aug 21, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆120Nov 26, 2025Updated 9 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆186Dec 14, 2019Updated 6 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆248Oct 16, 2025Updated 11 months ago
- IC implementation of Systolic Array for TPU☆371Oct 21, 2024Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- ☆31Aug 8, 2020Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆212Jun 25, 2020Updated 6 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆17May 17, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆25Apr 25, 2025Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆199Mar 20, 2024Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆52Jun 24, 2022Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆175May 10, 2025Updated last year
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆57Updated this week
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- Contains the code for the Flexus cycle-accurate simulator, used in QFlex.☆14Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆39Aug 13, 2024Updated 2 years ago
- A Rocket-based RISC-V superscalar in-order core☆42Aug 31, 2026Updated 3 weeks ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆13May 14, 2019Updated 7 years ago
- An AI accelerator implementation with Xilinx FPGA☆123Sep 3, 2026Updated 2 weeks ago
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆13Aug 26, 2023Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆162Jan 29, 2024Updated 2 years ago