thousrm / universal_NPU-CNN_acceleratorLinks
hardware design of universal NPU(CNN accelerator) for various convolution neural network
☆129Updated 4 months ago
Alternatives and similar repositories for universal_NPU-CNN_accelerator
Users that are interested in universal_NPU-CNN_accelerator are comparing it to the libraries listed below
Sorting:
- IC implementation of TPU☆127Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆197Updated 5 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆152Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆125Updated 5 months ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆76Updated last year
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆191Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆156Updated 5 years ago
- IC implementation of Systolic Array for TPU☆257Updated 8 months ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆102Updated 4 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- ☆113Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆121Updated 2 months ago
- ☆41Updated 4 years ago
- AMD University Program HLS tutorial☆99Updated 8 months ago
- ☆65Updated 6 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆79Updated last year
- Vitis HLS Library for FINN☆202Updated 3 weeks ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- ☆47Updated 2 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- AI Chip project☆32Updated 4 years ago