0x5b25 / CNN_CoreLinks
A CNN accelerator design inspired by MIT Eyeriss project
☆17Updated 3 years ago
Alternatives and similar repositories for CNN_Core
Users that are interested in CNN_Core are comparing it to the libraries listed below
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- ☆111Updated 4 years ago
- DMA controller for CNN accelerator☆13Updated 8 years ago
- A DNN Accelerator implemented with RTL.☆64Updated 4 months ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- ☆15Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago
- An OpenCL-Based FPGA Accelerator for Compressed YOLOv2☆37Updated 4 years ago
- ☆33Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- ☆65Updated 6 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆36Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆33Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆16Updated 6 years ago
- An LeNet RTL implement onto FPGA☆48Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago