A CNN accelerator design inspired by MIT Eyeriss project
☆20Aug 14, 2021Updated 4 years ago
Alternatives and similar repositories for CNN_Core
Users that are interested in CNN_Core are comparing it to the libraries listed below
Sorting:
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Dec 13, 2019Updated 6 years ago
- ☆13Aug 21, 2019Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- ☆125Jul 22, 2020Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Low level design of a chip built for optimizing/accelerating CNN classifiers over gray scale images.☆12May 14, 2019Updated 6 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆199Dec 15, 2017Updated 8 years ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- DMA controller for CNN accelerator☆14May 22, 2017Updated 8 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆45Sep 21, 2022Updated 3 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- EndoL2H: Deep Super-Resolution for Capsule Endoscopy☆12May 25, 2020Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆248Apr 10, 2023Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog☆11Dec 26, 2020Updated 5 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Jul 7, 2022Updated 3 years ago
- ☆10Jan 3, 2022Updated 4 years ago
- ☆11Aug 2, 2023Updated 2 years ago
- This repository is a collection of designs invloving FPGAs and AI technologies.☆14Jan 11, 2023Updated 3 years ago
- ☆19Dec 3, 2019Updated 6 years ago
- Accelerated Image Reconstruction using Generative Adversarial Networks on Cloud FPGAs☆11Aug 27, 2021Updated 4 years ago
- This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sen…☆17May 1, 2022Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆195Mar 20, 2024Updated 2 years ago
- PIMesh: Video-based in-bed human shape estimation from Pressure Images☆10Jan 5, 2026Updated 2 months ago
- ☆18Jun 10, 2016Updated 9 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆21May 27, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆221Dec 22, 2020Updated 5 years ago
- C++ RTL simulator for EIE(https://arxiv.org/abs/1602.01528)☆24Mar 17, 2021Updated 5 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆47Oct 14, 2022Updated 3 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆299Aug 16, 2018Updated 7 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆165Dec 13, 2020Updated 5 years ago