ChrisZonghaoLi / cnn_conv_acceleratorLinks
A Fix-pointed Rudimentary CNN Convolution Accelerator
☆16Updated 5 years ago
Alternatives and similar repositories for cnn_conv_accelerator
Users that are interested in cnn_conv_accelerator are comparing it to the libraries listed below
Sorting:
- RTL code for the DPU chip designed for irregular graphs☆13Updated 3 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- DMA controller for CNN accelerator☆14Updated 8 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Updated 3 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆60Updated 3 years ago
- Verilog implementation of Softmax function☆77Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆47Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- ☆17Updated 3 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Updated 4 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 6 years ago
- This project implements a convolution kernel based on vivado HLS on zcu104☆37Updated 5 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- ☆71Updated 7 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆16Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- HLS implemented systolic array structure☆41Updated 8 years ago
- ☆21Updated 3 years ago
- ☆38Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- This repository contains full code of Softmax Layer in Verilog☆20Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- ☆26Updated 3 years ago
- ☆20Updated 3 years ago