A Fix-pointed Rudimentary CNN Convolution Accelerator
☆16Oct 7, 2020Updated 5 years ago
Alternatives and similar repositories for cnn_conv_accelerator
Users that are interested in cnn_conv_accelerator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 4 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆10Jan 3, 2022Updated 4 years ago
- This repository is a collection of designs invloving FPGAs and AI technologies.☆14Jan 11, 2023Updated 3 years ago
- ☆19Dec 3, 2019Updated 6 years ago
- Simple test of ARM NEON code. Performs a blit to the framebuffer.☆15Jul 23, 2013Updated 12 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- ☆18Jun 10, 2016Updated 9 years ago
- A convolution based 3x3 GaussianBlur implementation using ARM NEON assembly engine☆10Jan 20, 2019Updated 7 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated last year
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆248Apr 10, 2023Updated 2 years ago
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 9 months ago
- ☆12Oct 8, 2021Updated 4 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆16Apr 17, 2021Updated 4 years ago
- Verilog implementation of pipelined cpu☆12Feb 8, 2021Updated 5 years ago
- ☆125Jul 22, 2020Updated 5 years ago
- 简单易用的微信小程序倒计时库☆15May 15, 2018Updated 7 years ago
- USB2.0 Device Controller IP Core☆15Aug 18, 2023Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆11Jun 28, 2020Updated 5 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆14Nov 4, 2022Updated 3 years ago
- ☆11Aug 2, 2023Updated 2 years ago
- The code for AIM2022 compressed image super-resolution☆11Nov 30, 2022Updated 3 years ago
- Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…☆13Mar 30, 2023Updated 2 years ago
- ☆11Oct 10, 2019Updated 6 years ago
- This repository is an excuse to learn about Convolutional Neural Networks by implementing one in FPGA. The main goal is to learn, and to …☆12Jul 12, 2020Updated 5 years ago
- Face recognition with loss of softmax, sphereface, cosface, arcface in pytorch of python3☆10Apr 27, 2020Updated 5 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆551Jan 5, 2019Updated 7 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Oct 2, 2019Updated 6 years ago
- Hardware accelerator for convolutional neural networks☆67Aug 9, 2022Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆199Dec 15, 2017Updated 8 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago