BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
☆63Updated 2 months ago
Alternatives and similar repositories for CNN-Accelerator-Based-on-Eyeriss-v2:
Users that are interested in CNN-Accelerator-Based-on-Eyeriss-v2 are comparing it to the libraries listed below
- ☆107Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆98Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- tpu-systolic-array-weight-stationary☆24Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆43Updated 2 years ago
- verilog实现systolic array及配套IO☆8Updated 4 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆32Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- ☆36Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆30Updated 2 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆43Updated last month
- ☆63Updated 6 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆37Updated 9 months ago
- ☆14Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆191Updated 2 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆11Updated 8 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆29Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆178Updated 7 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆31Updated 5 years ago
- ☆10Updated 3 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago