BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
☆51Updated 3 weeks ago
Alternatives and similar repositories for CNN-Accelerator-Based-on-Eyeriss-v2:
Users that are interested in CNN-Accelerator-Based-on-Eyeriss-v2 are comparing it to the libraries listed below
- ☆103Updated 4 years ago
- tpu-systolic-array-weight-stationary☆20Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆146Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- ☆63Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- ☆31Updated 5 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆14Updated 5 years ago
- ☆14Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆91Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆28Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆37Updated 7 months ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆27Updated 4 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Updated 6 years ago
- ☆28Updated 4 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆17Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago