BoooC / CNN-Accelerator-Based-on-Eyeriss-v2Links
A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
☆109Updated 2 months ago
Alternatives and similar repositories for CNN-Accelerator-Based-on-Eyeriss-v2
Users that are interested in CNN-Accelerator-Based-on-Eyeriss-v2 are comparing it to the libraries listed below
Sorting:
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- ☆118Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆172Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆227Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆192Updated last year
- IC implementation of Systolic Array for TPU☆280Updated 11 months ago
- ☆42Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆194Updated 7 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago
- General CNN_Accelerator design.卷积神经 网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆68Updated 7 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 5 years ago
- IC implementation of TPU☆132Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆41Updated 2 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆152Updated 7 months ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆27Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆45Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆21Updated last year
- FPGA based Vision Transformer accelerator (Harvard CS205)☆130Updated 7 months ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆163Updated last year
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆95Updated 8 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆35Updated 5 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆159Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆70Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Verilog implementation of Softmax function☆70Updated 3 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆12Updated last year