cea-wind / SimpleTPULinks
A FPGA Based CNN accelerator, following Google's TPU V1.
☆156Updated 5 years ago
Alternatives and similar repositories for SimpleTPU
Users that are interested in SimpleTPU are comparing it to the libraries listed below
Sorting:
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- ☆113Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆197Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆121Updated 2 months ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆105Updated 6 years ago
- IC implementation of Systolic Array for TPU☆257Updated 8 months ago
- ☆41Updated 4 years ago
- IC implementation of TPU☆127Updated 5 years ago
- CNN accelerator implemented with Spinal HDL☆150Updated last year
- 中文:☆101Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆35Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆346Updated last year
- ☆65Updated 6 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆183Updated last year
- A DNN Accelerator implemented with RTL.☆64Updated 6 months ago
- Vitis HLS Library for FINN☆202Updated 2 weeks ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆152Updated 2 years ago
- Verilog implementation of Softmax function☆67Updated 2 years ago
- ☆46Updated 7 years ago
- The second place winner for DAC-SDC 2020☆97Updated 3 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆112Updated 8 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆102Updated 4 months ago