arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2Links
☆115Updated 5 years ago
Alternatives and similar repositories for CNN-Accelerator-Implementation-based-on-Eyerissv2
Users that are interested in CNN-Accelerator-Implementation-based-on-Eyerissv2 are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆166Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆132Updated 4 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆100Updated last month
- Deep Learning Accelerator (Convolution Neural Networks)☆192Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆222Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆187Updated last year
- ☆42Updated 4 years ago
- IC implementation of Systolic Array for TPU☆273Updated 10 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆62Updated 6 months ago
- Hardware accelerator for convolutional neural networks☆53Updated 3 years ago
- IC implementation of TPU☆131Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆67Updated 8 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆40Updated last year
- Convolutional Neural Network Using High Level Synthesis☆88Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆158Updated 6 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆24Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆87Updated 7 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆128Updated 7 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆44Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- An FPGA Accelerator for Transformer Inference☆88Updated 3 years ago
- FPGA/AES/LeNet/VGG16☆108Updated 7 years ago
- Convolutional Neural Network RTL-level Design☆68Updated 3 years ago
- ☆66Updated 6 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago