arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
☆103Updated 4 years ago
Alternatives and similar repositories for CNN-Accelerator-Implementation-based-on-Eyerissv2:
Users that are interested in CNN-Accelerator-Implementation-based-on-Eyerissv2 are comparing it to the libraries listed below
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆146Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆177Updated 7 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆51Updated 3 weeks ago
- Convolutional accelerator kernel, target ASIC & FPGA☆185Updated last year
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- IC implementation of Systolic Array for TPU☆204Updated 4 months ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- ☆63Updated 6 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆157Updated 11 months ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- An LeNet RTL implement onto FPGA☆42Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆91Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆97Updated 6 years ago
- 3×3脉动阵列乘法器☆43Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆27Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆28Updated 2 years ago
- Verilog implementation of Softmax function☆59Updated 2 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆37Updated 7 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- ☆28Updated 4 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Simulating implement of vgg16 network on Zynq-7020 FPGA☆38Updated 6 years ago
- Convolutional Neural Network RTL-level Design☆48Updated 3 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆143Updated 9 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago