☆128Jul 22, 2020Updated 6 years ago
Alternatives and similar repositories for CNN-Accelerator-Implementation-based-on-Eyerissv2
Users that are interested in CNN-Accelerator-Implementation-based-on-Eyerissv2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- ☆14Aug 21, 2019Updated 7 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆266Apr 10, 2023Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆158Jul 22, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆212Jun 25, 2020Updated 6 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆227Dec 22, 2020Updated 5 years ago
- A CNN accelerator design inspired by MIT Eyeriss project☆20Aug 14, 2021Updated 5 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆15Aug 26, 2021Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆32Apr 7, 2025Updated last year
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 6 years ago
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 5 years ago
- Eyeriss Hardware Accelerator for Machine Learning☆13May 29, 2022Updated 4 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 4 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆36Jun 30, 2020Updated 6 years ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆393Sep 21, 2026Updated 3 weeks ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆181Mar 5, 2025Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- IC implementation of Systolic Array for TPU☆375Oct 21, 2024Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆95Apr 26, 2026Updated 5 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Dec 13, 2019Updated 6 years ago
- A scalable Eyeriss model in SystemC.☆36Jan 1, 2023Updated 3 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Feb 28, 2021Updated 5 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆22Dec 10, 2022Updated 3 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆47Sep 26, 2023Updated 3 years ago
- Berkeley's Spatial Array Generator☆1,507Updated this week
- Eyeriss chip simulator☆41Mar 6, 2020Updated 6 years ago
- Wraps the NVDLA project for Chipyard integration☆24Sep 2, 2025Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆248Oct 16, 2025Updated 11 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- IC implementation of TPU☆161Dec 18, 2019Updated 6 years ago
- 【 入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆201Apr 10, 2023Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆200Mar 20, 2024Updated 2 years ago
- ☆32Mar 31, 2025Updated last year
- Timeloop performs modeling, mapping and code-generation for tensor algebra workloads on various accelerator architectures.☆528Jul 26, 2026Updated 2 months ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago