VincentWang1998 / ai_on_chip_project1
tpu-systolic-array-weight-stationary
☆23Updated 3 years ago
Alternatives and similar repositories for ai_on_chip_project1:
Users that are interested in ai_on_chip_project1 are comparing it to the libraries listed below
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆56Updated last month
- ☆31Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆92Updated 3 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- Hardware accelerator for convolutional neural networks☆40Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆29Updated 2 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆15Updated 5 years ago
- syn script for DC Compiler☆12Updated 2 years ago
- ☆14Updated last year
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆97Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆47Updated 4 years ago
- A systolic array matrix multiplier☆24Updated 5 years ago
- ☆63Updated 6 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆31Updated last year
- AIChip 2021 project, NCKU☆18Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- ☆104Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆147Updated 5 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 3 years ago
- ☆33Updated 4 years ago
- A verilog implementation for Network-on-Chip☆72Updated 7 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆9Updated 4 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆16Updated last year