Alternatives and similar repositories for ai_on_chip_project1:

Users that are interested in ai_on_chip_project1 are comparing it to the libraries listed below

• Spiritator / FPGA_LeNet5_ws_8x8
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆11Updated 4 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆46Updated last week
• kuladeepsaireddy / OpenNoc
  ☆29Updated 5 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆27Updated 4 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆36Updated 2 years ago
• gju06051 / TPU_HW_Verilog
  ☆13Updated last year
• gem5-X / TiC-SAT
  ☆12Updated 8 months ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆81Updated 3 years ago
• suchuankai / CNN-hw-accelerator
  CNN hardware accelerator to accelerate quantized LeNet-5 model
  ☆28Updated last year
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆12Updated 4 years ago
• Giftwen / DC_script
  syn script for DC Compiler
  ☆12Updated 2 years ago
• hazooree / LeNet-CNN-Accelerator-Hardware-for-FPGA
  An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017
  ☆14Updated 5 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆26Updated 5 years ago
• wubinyi / Convolutional-Neural-Network-Accelerator
  Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).
  ☆20Updated 6 years ago
• KULeuven-MICAS / tinyvers
  TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.
  ☆15Updated last year
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆101Updated 4 years ago
• wzc810049078 / systolic-array-matrix-multiplier
  A systolic array matrix multiplier
  ☆24Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆89Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆62Updated 6 years ago
• gl9544 / vit_transformer_fpga
  ☆14Updated last year
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆24Updated 2 years ago
• ahirsharan / LSTM
  Single Long Short Term Memory (LSTM) cell : Verilog Implementation
  ☆30Updated 4 years ago
• AIC2021 / AIC2021_TPU_Template
  Template for project1 TPU
  ☆15Updated 3 years ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆33Updated last month
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆42Updated 5 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆141Updated 5 years ago
• dldldlfma / super_small_toy_tpu
  ☆20Updated 4 years ago