GATECH-EIC / ViTCoDLinks
[HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design
☆108Updated last year
Alternatives and similar repositories for ViTCoD
Users that are interested in ViTCoD are comparing it to the libraries listed below
Sorting:
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆94Updated 9 months ago
- ☆47Updated 3 years ago
- A co-design architecture on sparse attention☆52Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆46Updated last year
- ☆43Updated 6 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- ☆101Updated last year
- ☆29Updated last week
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆28Updated last year
- ViTALiTy (HPCA'23) Code Repository☆23Updated 2 years ago
- An FPGA Accelerator for Transformer Inference☆83Updated 3 years ago
- ☆35Updated 4 years ago
- Open-source of MSD framework☆16Updated last year
- [ASPLOS 2024] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators☆38Updated last year
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆121Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆57Updated 3 months ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated 11 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆54Updated 3 months ago
- ☆52Updated last year
- Computing in memory optimizes data handling by performing operations directly in memory, ideal for high-speed data processing needs. This…☆21Updated 7 months ago
- ☆27Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆54Updated this week
- RTL implementation of Flex-DPE.☆103Updated 5 years ago
- ☆59Updated 2 weeks ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆53Updated 2 months ago
- SDA: Low-Bit Stable Diffusion Acceleration on Edge FPGAs☆17Updated last year
- Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators☆81Updated last month
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆126Updated 4 months ago