Alternatives and similar repositories for ViTCoD

Users that are interested in ViTCoD are comparing it to the libraries listed below

• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆112Updated last year
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆52Updated last year
• hatsu3 / Sanger
  ☆48Updated 4 years ago
• pku-liang / Sanger
  A co-design architecture on sparse attention
  ☆53Updated 4 years ago
• sjtu-zhao-lab / SALO
  An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences
  ☆29Updated last year
• abdelfattah-lab / BitMoD-HPCA-25
  ☆51Updated 3 months ago
• cjg91 / trans-fat
  An FPGA Accelerator for Transformer Inference
  ☆91Updated 3 years ago
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆33Updated last week
• isakedo / DNNsim
  ☆35Updated 5 years ago
• jeffreyyu0602 / quantized-training
  ☆32Updated this week
• sharc-lab / Edge-MoE
  Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts
  ☆126Updated last year
• GATECH-EIC / ViTALiTy
  ViTALiTy (HPCA'23) Code Repository
  ☆23Updated 2 years ago
• clevercool / ANT-Quantization
  ☆111Updated last year
• leesou / H2-LLM-ISCA-2025
  H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference
  ☆72Updated 6 months ago
• SFU-HiAccel / HiSpMV
  [TRETS 2025][FPGA 2024] FPGA Accelerator for Imbalanced SpMV using HLS
  ☆15Updated 2 months ago
• CASR-HKU / MSD-FCCM23
  Open-source of MSD framework
  ☆16Updated 2 years ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• fffasttime / AnyPackingNet
  ☆29Updated 6 months ago
• witmemtech / CIM-Technical-Papers-Collection
  Computing in memory optimizes data handling by performing operations directly in memory, ideal for high-speed data processing needs. This…
  ☆27Updated 11 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆67Updated last month
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆68Updated last month
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆98Updated 9 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆87Updated last year
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆26Updated 3 months ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆97Updated 6 months ago
• mit-emze / cimloop
  ☆68Updated 3 weeks ago
• wangxy-2000 / pimsim-nn
  ☆58Updated last year
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆157Updated 8 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆40Updated 2 years ago
• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆44Updated 3 years ago