abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
☆228Updated 6 months ago
Alternatives and similar repositories for Systolic-array-implementation-in-RTL-for-TPU:
Users that are interested in Systolic-array-implementation-in-RTL-for-TPU are comparing it to the libraries listed below
- Convolutional accelerator kernel, target ASIC & FPGA☆191Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆155Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆98Updated 3 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆178Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆143Updated 2 weeks ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆98Updated 4 years ago
- verilog实现systolic array及配套IO☆8Updated 4 months ago
- ☆107Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆166Updated last year
- IC implementation of TPU☆121Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 5 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆148Updated 10 months ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆63Updated 2 months ago
- ☆147Updated 2 weeks ago
- AXI总线连接器☆97Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆176Updated last year
- CNN accelerator implemented with Spinal HDL☆148Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆144Updated last year
- ☆36Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- Implementation of CNN using Verilog☆212Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆71Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- 3×3脉动阵列乘法器☆44Updated 5 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆43Updated last month
- A FPGA Based CNN accelerator, following Google's TPU V1.☆149Updated 5 years ago
- AMD University Program HLS tutorial☆89Updated 5 months ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆201Updated last year
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆189Updated 4 years ago