abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
☆189Updated 4 months ago
Alternatives and similar repositories for Systolic-array-implementation-in-RTL-for-TPU:
Users that are interested in Systolic-array-implementation-in-RTL-for-TPU are comparing it to the libraries listed below
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆139Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆181Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆77Updated 3 years ago
- ☆100Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆173Updated 7 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆141Updated 8 months ago
- An AXI4 crossbar implementation in SystemVerilog☆131Updated 2 months ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆147Updated 10 months ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆66Updated last year
- CNN accelerator implemented with Spinal HDL☆144Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆167Updated 11 months ago
- Small-scale Tensor Processing Unit built on an FPGA☆149Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆80Updated 5 years ago
- ☆114Updated last week
- IC implementation of TPU☆98Updated 5 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆94Updated 6 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆62Updated 6 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆123Updated last year
- ☆60Updated 6 years ago
- AXI总线连接器☆94Updated 4 years ago
- Verilog implementation of Softmax function☆56Updated 2 years ago
- Implementation of CNN using Verilog☆206Updated 7 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆32Updated last week
- FPGA based Vision Transformer accelerator (Harvard CS205)☆103Updated last week
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆44Updated 5 months ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆178Updated 4 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆12Updated 9 months ago