leo47007 / TPU-Tensor-Processing-UnitLinks
IC implementation of TPU
☆125Updated 5 years ago
Alternatives and similar repositories for TPU-Tensor-Processing-Unit
Users that are interested in TPU-Tensor-Processing-Unit are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago
- AI Chip project☆32Updated 3 years ago
- ☆39Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆65Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- IC implementation of Systolic Array for TPU☆246Updated 7 months ago
- Small-scale Tensor Processing Unit built on an FPGA☆188Updated 5 years ago
- ☆111Updated 4 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆184Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆153Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆54Updated 4 years ago
- FPGA/AES/LeNet/VGG16☆103Updated 6 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆125Updated 3 months ago
- An AXI4 crossbar implementation in SystemVerilog☆156Updated 3 weeks ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆125Updated 7 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆192Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- verilog实现systolic array及配套IO☆8Updated 6 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆152Updated 11 months ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- AMD University Program HLS tutorial☆95Updated 7 months ago