IC implementation of TPU
☆156Dec 18, 2019Updated 6 years ago
Alternatives and similar repositories for TPU-Tensor-Processing-Unit
Users that are interested in TPU-Tensor-Processing-Unit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆55Jan 14, 2021Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆569Jan 5, 2019Updated 7 years ago
- IC implementation of Systolic Array for TPU☆364Oct 21, 2024Updated last year
- A FPGA Based CNN accelerator, following Google's TPU V1.☆175Jul 25, 2019Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- verilog实现TPU中的脉动阵列计算卷积的module☆173May 10, 2025Updated last year
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 5 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆175Jun 9, 2023Updated 3 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆272May 6, 2023Updated 3 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆759Dec 6, 2017Updated 8 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- ☆16Apr 24, 2023Updated 3 years ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆256Apr 10, 2023Updated 3 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆225Dec 22, 2020Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆200Dec 15, 2017Updated 8 years ago
- ☆128Jul 22, 2020Updated 5 years ago
- course design☆23Feb 28, 2018Updated 8 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RTL code for the DPU chip designed for irregular graphs☆14May 30, 2022Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆37Aug 28, 2025Updated 10 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- Eyeriss chip simulator☆41Mar 6, 2020Updated 6 years ago
- Systolic-array based Deep Learning Accelerator generator☆29Dec 11, 2020Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆50Jun 24, 2022Updated 4 years ago
- Berkeley's Spatial Array Generator☆1,365Updated this week
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆232Mar 8, 2020Updated 6 years ago
- ☆24May 14, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆18Feb 27, 2021Updated 5 years ago
- Matrix Multiply and Accumulate unit written in System Verilog☆15Feb 7, 2019Updated 7 years ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆451Dec 2, 2019Updated 6 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆34May 22, 2026Updated last month
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago