IC implementation of TPU
☆162Dec 18, 2019Updated 6 years ago
Alternatives and similar repositories for TPU-Tensor-Processing-Unit
Users that are interested in TPU-Tensor-Processing-Unit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆58Jan 14, 2021Updated 5 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆230Aug 4, 2019Updated 7 years ago
- AI Chip project☆35Jul 14, 2021Updated 5 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆583Jan 5, 2019Updated 7 years ago
- IC implementation of Systolic Array for TPU☆379Oct 21, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A FPGA Based CNN accelerator, following Google's TPU V1.☆179Jul 25, 2019Updated 7 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆181May 10, 2025Updated last year
- AIChip 2021 project, NCKU☆18May 6, 2021Updated 5 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆274May 6, 2023Updated 3 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆180Jun 9, 2023Updated 3 years ago
- Deploy llama2.c on the OpenLA500 SoC with custom AI accelerator (FPGA)☆24Jun 16, 2026Updated 4 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆53Jun 24, 2022Updated 4 years ago
- ☆15Apr 24, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Convolutional accelerator kernel, target ASIC & FPGA☆267Apr 10, 2023Updated 3 years ago
- npu☆13Sep 5, 2018Updated 8 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆806Dec 6, 2017Updated 8 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆39Aug 28, 2025Updated last year
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated 2 months ago
- An AI accelerator implementation with Xilinx FPGA☆136Updated this week
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆19Feb 27, 2021Updated 5 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆28Jun 21, 2024Updated 2 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆228Dec 22, 2020Updated 5 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆202Dec 15, 2017Updated 8 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 5 years ago
- Accelerator for LLM Based on Chisel3☆15Jul 16, 2026Updated 3 months ago
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆394Sep 21, 2026Updated last month
- Eyeriss chip simulator☆42Mar 6, 2020Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- Antmicro's open hardware baseboard for the Google Coral i.MX8 + Edge TPU SoM☆80Aug 7, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago
- HiPU200 open-source version is a DNN accelerator, using RISC-V instruction set and customized vector/matrix extension.☆10Jan 7, 2022Updated 4 years ago
- Berkeley's Spatial Array Generator☆1,535Updated this week
- eyeriss-chisel3☆41May 2, 2022Updated 4 years ago
- ☆127Jul 22, 2020Updated 6 years ago
- 在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。☆337Aug 16, 2018Updated 8 years ago
- SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations☆22Apr 12, 2026Updated 6 months ago