IC implementation of TPU
☆148Dec 18, 2019Updated 6 years ago
Alternatives and similar repositories for TPU-Tensor-Processing-Unit
Users that are interested in TPU-Tensor-Processing-Unit are comparing it to the libraries listed below
Sorting:
- Small-scale Tensor Processing Unit built on an FPGA☆219Aug 4, 2019Updated 6 years ago
- ☆49Jan 14, 2021Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- Implementation of a Tensor Processing Unit for embedded systems and the IoT.☆543Jan 5, 2019Updated 7 years ago
- IC implementation of Systolic Array for TPU☆339Oct 21, 2024Updated last year
- AIChip 2021 project, NCKU☆17May 6, 2021Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆159May 10, 2025Updated 9 months ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆172Jul 25, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆171Jun 9, 2023Updated 2 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Free TPU for FPGA with compiler supporting Pytorch/Caffe/Darknet/NCNN. An AI processor for using Xilinx FPGA to solve image classificatio…☆273May 6, 2023Updated 2 years ago
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆735Dec 6, 2017Updated 8 years ago
- An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"☆218Dec 22, 2020Updated 5 years ago
- ☆14Apr 24, 2023Updated 2 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs.☆31Aug 28, 2025Updated 6 months ago
- A Toy-Purpose TPU Simulator☆21Jun 7, 2024Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago
- ☆124Jul 22, 2020Updated 5 years ago
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- a student trainning project for HLS and transformer☆11Oct 19, 2022Updated 3 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 10 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆82Apr 30, 2019Updated 6 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆245Apr 10, 2023Updated 2 years ago
- ☆21May 14, 2025Updated 9 months ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- course design☆23Feb 28, 2018Updated 8 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- ☆10Dec 15, 2023Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Updated this week
- HLS for Networks-on-Chip☆39Feb 18, 2021Updated 5 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆443Dec 2, 2019Updated 6 years ago