suchuankai / CNN-hw-acceleratorLinks
CNN hardware accelerator to accelerate quantized LeNet-5 model
☆36Updated last year
Alternatives and similar repositories for CNN-hw-accelerator
Users that are interested in CNN-hw-accelerator are comparing it to the libraries listed below
Sorting:
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆14Updated 10 months ago
- ☆111Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆45Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆33Updated 4 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆73Updated 3 months ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆38Updated 10 months ago
- verilog实现systolic array及配套IO☆8Updated 6 months ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆31Updated 2 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆160Updated 5 years ago
- ☆15Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆22Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆117Updated 3 weeks ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆11Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连 接层等硬件加速计算。☆48Updated 3 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- ☆65Updated 6 years ago
- ☆39Updated 4 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆205Updated 2 years ago
- ☆33Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆55Updated 3 years ago
- 使用FPGA实现CNN模型☆15Updated 5 years ago
- ☆33Updated 8 months ago