CNN hardware accelerator to accelerate quantized LeNet-5 model
☆44Sep 26, 2023Updated 2 years ago
Alternatives and similar repositories for CNN-hw-accelerator
Users that are interested in CNN-hw-accelerator are comparing it to the libraries listed below
Sorting:
- Tensor Processing Unit implementation in Verilog☆13Mar 18, 2025Updated 11 months ago
- Hardware accelerator for convolutional neural networks☆66Aug 9, 2022Updated 3 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆35Apr 13, 2024Updated last year
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Nov 4, 2022Updated 3 years ago
- 基于Xilinx FPGA的通用型 CNN卷积神经网络加速器，本设计基于KV260板卡，MpSoC架构均可移植☆18Dec 13, 2024Updated last year
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- Hardware and Software Co-design implementations☆15Dec 5, 2019Updated 6 years ago
- bitfusion verilog implementation☆12Feb 21, 2022Updated 4 years ago
- ☆12Jul 24, 2018Updated 7 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 5 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆28Jul 31, 2019Updated 6 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- ☆18Oct 3, 2024Updated last year
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Jun 5, 2023Updated 2 years ago
- ☆19Sep 12, 2022Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Jun 30, 2020Updated 5 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- ☆18Nov 11, 2025Updated 3 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆18Aug 19, 2024Updated last year
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆45Jun 24, 2022Updated 3 years ago
- A DNN Accelerator implemented with RTL.☆69Jan 9, 2025Updated last year
- In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…☆23Aug 28, 2024Updated last year
- Deep learning accelerator for convolutional layer (convolution operation) and fully-connected layer(matrix-multiplication).☆20Nov 18, 2018Updated 7 years ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆180Apr 10, 2023Updated 2 years ago
- FPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS☆16Mar 1, 2021Updated 5 years ago
- ☆16Mar 23, 2023Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Jun 22, 2021Updated 4 years ago
- ☆124Jul 22, 2020Updated 5 years ago
- Framework for radix encoded SNN on FPGA☆18Dec 7, 2021Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆23May 20, 2019Updated 6 years ago
- A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacemen…☆17Sep 16, 2018Updated 7 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- An LeNet RTL implement onto FPGA☆50May 4, 2018Updated 7 years ago
- An automated HDC platform☆11Feb 28, 2026Updated last week
- ☆46Apr 8, 2023Updated 2 years ago