jiaaom / HPDLA
Systolic-array based Deep Learning Accelerator generator
☆24Updated 4 years ago
Alternatives and similar repositories for HPDLA
Users that are interested in HPDLA are comparing it to the libraries listed below
Sorting:
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 2 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- ☆70Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆64Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- ☆35Updated 4 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- ☆27Updated 5 years ago
- A static dataflow CGRA with dynamic dataflow execution capability☆10Updated 3 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆28Updated 3 years ago
- ☆57Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆71Updated 2 years ago
- ☆33Updated 6 years ago
- CNN Accelerator in Frequency Domain☆12Updated 5 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆20Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- CNN accelerator☆27Updated 7 years ago
- ☆65Updated 3 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Template for project1 TPU☆18Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆26Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- A collection of tutorials for the fpgaConvNet framework.☆39Updated 7 months ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 11 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago