jiaaom / HPDLALinks
Systolic-array based Deep Learning Accelerator generator
☆25Updated 4 years ago
Alternatives and similar repositories for HPDLA
Users that are interested in HPDLA are comparing it to the libraries listed below
Sorting:
- ☆65Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- ☆58Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- ☆66Updated 3 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- ☆71Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆53Updated 10 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆106Updated 7 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- System Verilog code describing a fully combinational binarized neural network.☆34Updated 7 years ago
- ☆34Updated 6 years ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- IC implementation of TPU☆128Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 7 years ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆87Updated 2 months ago
- ☆72Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Verilog implementation of Softmax function☆67Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago