Systolic-array based Deep Learning Accelerator generator
☆28Dec 11, 2020Updated 5 years ago
Alternatives and similar repositories for HPDLA
Users that are interested in HPDLA are comparing it to the libraries listed below
Sorting:
- Systolic array based hardware for Image processing on the SPARTAN-6 FPGA☆13May 26, 2016Updated 9 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆27Jul 4, 2019Updated 6 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Jan 2, 2021Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆245Apr 10, 2023Updated 2 years ago
- A systolic array matrix multiplier☆30Sep 11, 2019Updated 6 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Jun 5, 2020Updated 5 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- https://nnsmith-asplos.rtfd.io Artifact of "NNSmith: Generating Diverse and Valid Test Cases for Deep Learning Compilers" ASPLOS'23☆11Mar 29, 2023Updated 2 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- ☆13Jul 25, 2024Updated last year
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆14Aug 25, 2023Updated 2 years ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 5 years ago
- LSTM neural network (verilog)☆15Dec 5, 2018Updated 7 years ago
- CNN Accelerator in Frequency Domain☆12Feb 22, 2020Updated 6 years ago
- Digital Design Lab Spring 2019 Final Project☆13Jun 17, 2019Updated 6 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Jan 12, 2021Updated 5 years ago
- AFP is a hardware-friendly quantization framework for DNNs, which is contributed by Fangxin Liu and Wenbo Zhao.☆13Nov 8, 2021Updated 4 years ago
- hardware (ASIC) DEFLATE designed for low-latency page-granularity memory compression and implemented in Chisel☆16Nov 15, 2024Updated last year
- ☆19Mar 21, 2023Updated 2 years ago
- ES-203 Computer Organization & Architecture CNN on FPGA board☆17Feb 23, 2022Updated 4 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆207Jun 25, 2020Updated 5 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 7 years ago
- Wraps the NVDLA project for Chipyard integration☆22Sep 2, 2025Updated 6 months ago
- Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated☆235Dec 22, 2025Updated 2 months ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆23Jul 29, 2022Updated 3 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆18Jul 9, 2024Updated last year
- LCAI-TIHU SW is a software stack of the AI inference processor based on RISC-V☆23Dec 14, 2022Updated 3 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- ZyncMV is an open source machine/computer vision platform using the Xilinx Zync FPGA+ ARM Cortex A9 SoC☆20Feb 12, 2017Updated 9 years ago
- ☆21May 14, 2025Updated 9 months ago
- A DSL for Systolic Arrays☆83Dec 14, 2018Updated 7 years ago
- Model SAR ADC with python!☆22Jul 8, 2022Updated 3 years ago
- An automated HDC platform☆11Updated this week
- Small-scale Tensor Processing Unit built on an FPGA☆219Aug 4, 2019Updated 6 years ago
- Template for project1 TPU☆23May 1, 2021Updated 4 years ago
- IC implementation of Systolic Array for TPU☆339Oct 21, 2024Updated last year
- Curated content for DNN approximation, acceleration ... with a focus on hardware accelerator and deployment☆27May 15, 2024Updated last year
- In this repository, we explore model compression for transformer architectures via quantization. We specifically explore quantization awa…☆24May 14, 2021Updated 4 years ago