Spiritator / FPGA_LeNet5_ws_8x8Links
FPGA implement of 8x8 weight stationary systolic array DNN accelerator
☆12Updated 4 years ago
Alternatives and similar repositories for FPGA_LeNet5_ws_8x8
Users that are interested in FPGA_LeNet5_ws_8x8 are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆17Updated 2 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- Hardware accelerator for convolutional neural networks☆49Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 6 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆129Updated 3 months ago
- ☆113Updated 5 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆23Updated last year
- C++ code for HLS FPGA implementation of transformer☆17Updated 11 months ago
- This project is to design yolo AI accelerator in verilog HDL.☆21Updated 10 months ago
- ☆14Updated 2 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆95Updated last month
- Open-source of MSD framework☆16Updated last year
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆20Updated 4 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆12Updated 2 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆34Updated 5 years ago
- a Computing In Memory emULATOR framework☆13Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆10Updated 3 years ago
- ☆14Updated 3 years ago
- ☆44Updated 2 years ago
- eyeriss-chisel3☆41Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago