Spiritator / FPGA_LeNet5_ws_8x8Links
FPGA implement of 8x8 weight stationary systolic array DNN accelerator
☆16Updated 4 years ago
Alternatives and similar repositories for FPGA_LeNet5_ws_8x8
Users that are interested in FPGA_LeNet5_ws_8x8 are comparing it to the libraries listed below
Sorting:
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆42Updated 2 years ago
- ☆15Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆18Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆64Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆40Updated last year
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- ☆124Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆41Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Updated 6 years ago
- A systolic array matrix multiplier☆30Updated 6 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆122Updated last year
- Open-source of MSD framework☆16Updated 2 years ago
- Arrhythmia Detection Using Algorithm and Hardware Co-design for Neural Network Inference Accelerators☆16Updated 2 years ago
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆31Updated last year
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆21Updated 6 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆133Updated 6 months ago
- High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.☆41Updated last year
- ☆72Updated 7 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆30Updated last year
- A DNN Accelerator implemented with RTL.☆68Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆179Updated 6 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Updated 3 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆154Updated 8 months ago
- verilog实现systolic array及配套IO☆11Updated last year
- An FPGA Accelerator for Transformer Inference☆93Updated 3 years ago
- A collection of tutorials for the fpgaConvNet framework.☆48Updated last year
- ☆19Updated 3 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Updated 6 years ago