GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
☆153Updated 4 months ago
Alternatives and similar repositories for FPGA-CNN-accelerator-based-on-systolic-array:
Users that are interested in FPGA-CNN-accelerator-based-on-systolic-array are comparing it to the libraries listed below
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆137Updated last year
- 2023集创赛紫光同创杯一等奖项目☆104Updated last year
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的,只有主干网络部署在fpga上,片上资源无法支持整个网络所需资源,建议添加外部存储及DDR☆88Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆67Updated this week
- ☆217Updated 11 months ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆39Updated 2 weeks ago
- some interesting demos for starters☆72Updated 2 years ago
- FPGA☆151Updated 8 months ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago
- 【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码☆73Updated 2 years ago
- FPGA实现简单的图像处理算法☆41Updated last year
- FPGA project☆215Updated 2 years ago
- Convolutional Neural Network RTL-level Design☆48Updated 3 years ago
- CPU Design Based on RISCV ISA☆95Updated 9 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆33Updated 2 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆172Updated last year
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆13Updated 10 months ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆196Updated last year
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆77Updated 3 years ago
- CNN accelerator implemented with Spinal HDL☆146Updated last year
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆135Updated 5 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆90Updated 3 years ago
- 该作品为2024年FPGA创新设计大赛(上海安路科技赛道)国一作品☆19Updated last month
- ☆32Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆185Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆138Updated 4 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆157Updated 11 months ago
- 【2022集创赛】Arm杯一等奖作品:Cortex-M0智能娱乐收音机 开源项目☆27Updated 2 years ago