2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实 现不同的计算效率。
☆242Oct 16, 2025Updated 7 months ago
Alternatives and similar repositories for FPGA-CNN-accelerator-based-on-systolic-array
Users that are interested in FPGA-CNN-accelerator-based-on-systolic-array are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 2023集创赛紫光同创杯一等奖项目☆176Jan 7, 2024Updated 2 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆28May 20, 2019Updated 7 years ago
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 11 months ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆42Nov 27, 2022Updated 3 years ago
- 第八届集创赛紫光同创杯音频处理国家二等奖☆26Oct 15, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- 基于FPGA的cifar-10二维卷积识别任务☆12Sep 8, 2022Updated 3 years ago
- 网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR☆148Jul 20, 2023Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆169May 10, 2025Updated last year
- 2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition☆22Dec 2, 2024Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆255Apr 10, 2023Updated 3 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛（高云赛道）项目，题目基于高云FPGA的多路网络视频监控编码系统。☆70Dec 11, 2023Updated 2 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆280Apr 1, 2024Updated 2 years ago
- ☆13Aug 2, 2023Updated 2 years ago
- ☆14Aug 23, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- PC-side code for PacGoc, enterprise grand prize-winning work at PangoMirco Cup CICC 2024. [第八届集创赛紫光同创杯企业大奖获奖作品]☆19Oct 12, 2024Updated last year
- IC implementation of Systolic Array for TPU☆357Oct 21, 2024Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆198Mar 20, 2024Updated 2 years ago
- Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database☆594Feb 19, 2021Updated 5 years ago
- verilog实现systolic array及配套IO☆13Dec 2, 2024Updated last year
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆172Mar 5, 2025Updated last year
- FPGA Innovation Design Competition：RISC-V Processor-based Hardware and Software Design in PGL22G☆12Sep 1, 2023Updated 2 years ago
- ☆73Dec 12, 2018Updated 7 years ago
- ☆33Aug 23, 2023Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆125Jul 22, 2020Updated 5 years ago
- Eyeriss‑V1 CNN Hardware Accelerator (Verilog) fully parametric. This repository contains the complete Verilog implementation of a functio…☆30Apr 7, 2025Updated last year
- 3×3脉动阵列乘法器☆50Sep 18, 2019Updated 6 years ago
- 2024年全国大学生嵌入式芯片与系统设计竞赛 FPGA创新设计赛道 国一+易灵思创新杯获奖作品 Ultra-Vision （基于Ti60F225的无极缩放算法实现）☆91Mar 19, 2025Updated last year
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆193Apr 10, 2023Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 4 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆371May 2, 2023Updated 3 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆250Mar 24, 2024Updated 2 years ago
- 使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用☆587Jun 18, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Apr 10, 2020Updated 6 years ago
- a Real-time image recognition project with RTL accelerator and ZYNQ Architecture☆67Apr 8, 2024Updated 2 years ago
- Deep Learning Accelerator (Convolution Neural Networks)☆199Dec 15, 2017Updated 8 years ago
- This repository is used to store RTL code for combining a single video source from multiple video sources.☆18Oct 28, 2024Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆165Dec 13, 2020Updated 5 years ago
- A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard☆915Jul 29, 2024Updated last year
- This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model archite…☆34Sep 4, 2023Updated 2 years ago