Alternatives and similar repositories for xkDLA:

Users that are interested in xkDLA are comparing it to the libraries listed below

• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• pulp-platform / fpu
  ☆41Updated 6 years ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 4 months ago
• Aperture-Electronic / Realtime-Bicubic-16X-SuperResolution-IP
  APV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
  ☆22Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week
• pulp-platform / ITA
  ☆37Updated 3 months ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆9Updated last year
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆37Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆59Updated last year
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆43Updated 2 years ago
• kkiningh / cs231n-project
  CNN accelerator
  ☆27Updated 7 years ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆27Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆22Updated 5 months ago
• yuhsaun-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆15Updated this week
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 5 years ago