Alternatives and similar repositories for xkDLA

Users that are interested in xkDLA are comparing it to the libraries listed below

• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆42Updated 2 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆53Updated 4 years ago
• pulp-platform / fpu
  ☆53Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago
• Nuclei-Software / e603_hbird
  RV64GC Linux Capable RISC-V Core
  ☆28Updated 2 weeks ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 3 months ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆12Updated 2 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆29Updated 2 months ago
• pulp-platform / ITA
  ☆47Updated 4 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆18Updated 6 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆19Updated 3 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆63Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 3 years ago
• pulp-platform / axi_llc
  ☆30Updated last week
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• oprecomp / DDR4_controller
  ☆64Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Updated 4 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆57Updated 10 months ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆59Updated 2 weeks ago