Alternatives and similar repositories for xkDLA

Users that are interested in xkDLA are comparing it to the libraries listed below

• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆55Updated 4 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆72Updated 7 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆17Updated 7 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆14Updated 8 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆79Updated 2 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆34Updated last month
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆15Updated 3 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆67Updated 6 years ago
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆52Updated 6 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆20Updated 8 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆12Updated 2 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• pulp-platform / ITA
  ☆63Updated 9 months ago
• chenhaoc / cnnhwpe
  ☆66Updated 3 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 8 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 10 months ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• Zaoldyeckk / High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
  This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…
  ☆54Updated 7 years ago
• oprecomp / DDR4_controller
  ☆70Updated 4 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆25Updated 4 years ago
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆21Updated 3 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆21Updated 6 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆28Updated 2 weeks ago