Alternatives and similar repositories for xkDLA

Users that are interested in xkDLA are comparing it to the libraries listed below

• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆41Updated 2 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆34Updated 7 years ago
• pulp-platform / fpu
  ☆51Updated 6 years ago
• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆16Updated 6 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• pulp-platform / ITA
  ☆47Updated 2 months ago
• ljgibbslf / basic_cache_core
  ☆29Updated 4 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 8 years ago
• oprecomp / DDR4_controller
  ☆61Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆53Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆58Updated last week
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• stellagarden / EE405-Advanced-Digital-Systems-Design
  Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator
  ☆10Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆53Updated last year
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆21Updated 2 months ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 8 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆41Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆65Updated 6 years ago
• lycfly / EasyNPU
  A small Neural Network Processor for Edge devices.
  ☆11Updated 2 years ago
• BoChen-Ye / Tiny_LeViT_Hardware_Accelerator
  This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
  ☆20Updated 11 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆58Updated 2 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆43Updated 2 years ago
• scratch-gpu / MIAOW2
  MIAOW2.0 FPGA implementable design
  ☆12Updated 7 years ago
• Starrynightzyq / soNN
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆28Updated 4 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆18Updated 2 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆17Updated 5 years ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆24Updated 6 years ago