MPSLab-ASU / dMazeRunner
dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
☆45Updated 3 years ago
Alternatives and similar repositories for dMazeRunner:
Users that are interested in dMazeRunner are comparing it to the libraries listed below
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆28Updated last year
- ☆26Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- ☆16Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- ☆35Updated 4 years ago
- ☆25Updated 3 years ago
- ☆10Updated 2 years ago
- agile hardware-software co-design☆46Updated 3 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆38Updated 6 years ago
- ☆39Updated 10 months ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- EQueue Dialect☆40Updated 3 years ago
- Heterogenous ML accelerator☆18Updated 7 months ago
- ☆33Updated 3 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆79Updated last year
- ☆50Updated last month
- ☆14Updated last year
- ☆30Updated last month
- ☆33Updated 6 years ago
- ☆23Updated 4 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- ☆71Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆45Updated 2 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated 2 weeks ago
- A graph linear algebra overlay☆51Updated 2 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆29Updated 6 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago