ryaanluke / DNN-Hardware-AcceleratorLinks
SystemVerilog files for lab project on a DNN hardware accelerator
☆16Updated 4 years ago
Alternatives and similar repositories for DNN-Hardware-Accelerator
Users that are interested in DNN-Hardware-Accelerator are comparing it to the libraries listed below
Sorting:
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆163Updated 5 years ago
- CNN hardware accelerator to accelerate quantized LeNet-5 model☆38Updated last year
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆83Updated 4 months ago
- ☆113Updated 4 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆121Updated 2 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆216Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆103Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆47Updated 2 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- 3×3脉动阵列乘法器☆45Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆33Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆34Updated 5 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆41Updated 2 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆155Updated last year
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆17Updated 11 months ago
- A verilog implementation for Network-on-Chip☆74Updated 7 years ago
- verilog实现systolic array及配套IO☆9Updated 7 months ago
- ☆10Updated 3 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- ☆15Updated last year
- Deep Learning Accelerator (Convolution Neural Networks)☆188Updated 7 years ago
- AXI总线连接器☆100Updated 5 years ago
- ☆34Updated 6 years ago
- ☆17Updated last year
- Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.☆21Updated 4 years ago
- ☆41Updated 4 years ago
- General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。☆56Updated 4 months ago
- achieve softmax in PYNQ with heterogeneous computing.☆64Updated 6 years ago
- IC implementation of Systolic Array for TPU☆257Updated 8 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago