Alternatives and similar repositories for timeloop

Users that are interested in timeloop are comparing it to the libraries listed below

• maestro-project / maestro
  An analytical cost model evaluating DNN mappings (dataflows and tiling).
  ☆232Updated last year
• scalesim-project / SCALE-Sim
  Repository to host and maintain SCALE-Sim code
  ☆349Updated last month
• Accelergy-Project / accelergy
  Accelergy is an energy estimation infrastructure for accelerator energy estimations
  ☆149Updated 4 months ago
• ARM-software / SCALE-Sim
  ☆365Updated 2 years ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆225Updated 2 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆278Updated last year
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
  ☆341Updated last year
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆104Updated 5 months ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆139Updated 3 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆157Updated this week
• accel-sim / accel-sim-framework
  This is the top-level repository for the Accel-Sim framework.
  ☆481Updated last week
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆160Updated last month
• areuther / ai-accelerators
  CSV spreadsheets and other material for AI accelerator survey papers
  ☆179Updated last year
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆149Updated 7 months ago
• stanford-mast / nn_dataflow
  Explore the energy-efficient dataflow scheduling for neural networks.
  ☆227Updated 5 years ago
• cornell-zhang / allo
  Allo: A Programming Model for Composable Accelerator Design
  ☆281Updated last week
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆112Updated 5 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• BRTResearch / AIChip_Paper_List
  ☆643Updated 4 years ago
• harvard-acc / ALADDIN
  A pre-RTL, power-performance model for fixed-function accelerators
  ☆180Updated last year
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆248Updated 2 years ago
• HewlettPackard / cacti
  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
  ☆492Updated last year
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆194Updated 9 months ago
• apache / tvm-vta
  Open, Modular, Deep Learning Accelerator
  ☆310Updated last year
• SET-Scheduling-Project / SET-ISCA2023
  The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.
  ☆75Updated 6 months ago
• booksim / booksim2
  BookSim 2.0
  ☆368Updated last year
• mit-emze / cimloop
  ☆66Updated this week
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆366Updated 8 months ago
• hsharma35 / bitfusion
  Simulator for BitFusion
  ☆101Updated 5 years ago
• wangxy-2000 / pimsim-nn
  ☆57Updated last year