Alternatives and similar repositories for timeloop

Users that are interested in timeloop are comparing it to the libraries listed below

• scalesim-project / SCALE-Sim
  Repository to host and maintain SCALE-Sim code
  ☆411Updated last week
• maestro-project / maestro
  An analytical cost model evaluating DNN mappings (dataflows and tiling).
  ☆247Updated last year
• ARM-software / SCALE-Sim
  ☆377Updated 2 years ago
• cornell-zhang / heterocl
  HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)
  ☆342Updated last year
• Accelergy-Project / accelergy
  Accelergy is an energy estimation infrastructure for accelerator energy estimations
  ☆155Updated 8 months ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆236Updated 3 years ago
• UIUC-ChenLab / scalehls
  A scalable High-Level Synthesis framework on MLIR
  ☆288Updated last year
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆181Updated 2 weeks ago
• areuther / ai-accelerators
  CSV spreadsheets and other material for AI accelerator survey papers
  ☆189Updated 2 months ago
• cornell-zhang / allo
  Allo Accelerator Design and Programming Framework (PLDI'24)
  ☆343Updated this week
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆145Updated 7 months ago
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆162Updated this week
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆184Updated last month
• stanford-mast / nn_dataflow
  Explore the energy-efficient dataflow scheduling for neural networks.
  ☆233Updated 5 years ago
• accel-sim / accel-sim-framework
  This is the top-level repository for the Accel-Sim framework.
  ☆561Updated last week
• harvard-acc / ALADDIN
  A pre-RTL, power-performance model for fixed-function accelerators
  ☆184Updated 2 years ago
• harvard-acc / gem5-aladdin
  End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.
  ☆256Updated 3 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• HewlettPackard / cacti
  An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model
  ☆528Updated last year
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆114Updated 10 months ago
• booksim / booksim2
  BookSim 2.0
  ☆398Updated last year
• BRTResearch / AIChip_Paper_List
  ☆653Updated 5 years ago
• SAITPublic / PIMSimulator
  Processing-In-Memory (PIM) Simulator
  ☆221Updated last year
• mit-emze / cimloop
  ☆84Updated last month
• apache / tvm-vta
  Open, Modular, Deep Learning Accelerator
  ☆327Updated last year
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• harvard-acc / smaug
  SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin
  ☆114Updated 3 years ago
• vineodd / PIMSim
  PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
  ☆213Updated 2 years ago
• wangxy-2000 / pimsim-nn
  ☆58Updated last year
• spcl / gemm_hls
  Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
  ☆374Updated last year