pku-liang / SangerView external linksLinks
A co-design architecture on sparse attention
☆55Aug 23, 2021Updated 4 years ago
Alternatives and similar repositories for Sanger
Users that are interested in Sanger are comparing it to the libraries listed below
Sorting:
- ViTALiTy (HPCA'23) Code Repository☆23Mar 13, 2023Updated 2 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆127Jun 27, 2023Updated 2 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆31Mar 7, 2024Updated last year
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆56Nov 22, 2023Updated 2 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆132May 10, 2024Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆122Aug 27, 2024Updated last year
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆108Jun 19, 2024Updated last year
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆184Jan 8, 2026Updated last month
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- ☆48Aug 23, 2021Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Dec 14, 2019Updated 6 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆85Aug 28, 2023Updated 2 years ago
- Code for "CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction" on CIFAR-10/100.☆14Dec 10, 2021Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- An HBM FPGA based SpMV Accelerator☆17Aug 29, 2024Updated last year
- ☆42Jun 30, 2024Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Jul 26, 2024Updated last year
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- [TECS'23] A project on the co-design of Accelerators and CNNs.☆21Dec 10, 2022Updated 3 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆82Mar 12, 2025Updated 11 months ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆21Mar 20, 2025Updated 10 months ago
- STONNE: A Simulation Tool for Neural Networks Engines☆145Jun 16, 2025Updated 7 months ago
- FRAME: Fast Roofline Analytical Modeling and Estimation☆39Oct 13, 2023Updated 2 years ago
- An analytical framework that models hardware dataflow of tensor applications on spatial architectures using the relation-centric notation…☆87Apr 28, 2024Updated last year
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆73Sep 29, 2025Updated 4 months ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆125Jan 20, 2025Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆182Jan 23, 2026Updated 3 weeks ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆75Updated this week
- GPGPU-Sim 中文注释版代码，包含 GPGPU-Sim 模拟器的最新版代码，经过中文注释，以帮助中文用户更好地理解和使用该模拟器。☆28Dec 18, 2024Updated last year
- NPUsim: Full-Model, Cycle-Level, and Value-Aware Simulator for DNN Accelerators☆46Jan 2, 2025Updated last year
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated last year
- ☆12Sep 18, 2024Updated last year
- ☆224Oct 24, 2025Updated 3 months ago
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆66Apr 12, 2024Updated last year
- This is a series of quick start guide of Vitis HLS tool in Chinese. It explains the basic concepts and the most important optimize techni…☆25Nov 9, 2022Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆47Aug 8, 2022Updated 3 years ago
- Hardware accelerator for convolutional neural networks☆65Aug 9, 2022Updated 3 years ago