A co-design architecture on sparse attention
☆55Aug 23, 2021Updated 5 years ago
Alternatives and similar repositories for Sanger
Users that are interested in Sanger are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆136Jun 27, 2023Updated 3 years ago
- ViTALiTy (HPCA'23) Code Repository☆25Mar 13, 2023Updated 3 years ago
- An efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences☆34Mar 7, 2024Updated 2 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆63Nov 22, 2023Updated 2 years ago
- ☆48Aug 23, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆142Aug 27, 2024Updated 2 years ago
- HLS project modeling various sparse accelerators.☆12Jan 11, 2022Updated 4 years ago
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆144May 10, 2024Updated 2 years ago
- MICRO 2024 Evaluation Artifact for FuseMax☆19Aug 26, 2024Updated 2 years ago
- The framework for the paper "Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators" in ISCA 2023.☆87Mar 12, 2025Updated last year
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 5 years ago
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆218Oct 23, 2026Updated last week
- NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing☆133Jun 19, 2024Updated 2 years ago
- bitfusion verilog implementation☆13Feb 21, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Code for "CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction" on CIFAR-10/100.☆14Dec 10, 2021Updated 4 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆56Mar 24, 2024Updated 2 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆88Aug 28, 2023Updated 3 years ago
- STONNE: A Simulation Tool for Neural Networks Engines☆156Jun 16, 2025Updated last year
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆24Oct 1, 2022Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆187Dec 14, 2019Updated 6 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆14May 9, 2022Updated 4 years ago
- Attentionlego☆13Jan 24, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆205Oct 11, 2026Updated 3 weeks ago
- Research and Materials on Hardware implementation of Transformer Model☆313Oct 28, 2026Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆96Apr 26, 2026Updated 6 months ago
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆21Jul 9, 2024Updated 2 years ago
- ☆296Oct 24, 2025Updated last year
- Simulator for BitFusion☆104Aug 6, 2020Updated 6 years ago
- ☆45Jun 30, 2024Updated 2 years ago
- MICRO22 artifact evaluation for Sparseloop☆47Aug 8, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆10Sep 14, 2023Updated 3 years ago
- Repository to host and maintain SCALE-Sim code☆541Jun 28, 2026Updated 4 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆96Aug 11, 2026Updated 2 months ago
- NeuroSpector: Dataflow and Mapping Optimizer for Deep Neural Network Accelerators☆23Mar 20, 2025Updated last year
- ☆14Jun 18, 2025Updated last year
- ☆169Jun 24, 2024Updated 2 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆17Aug 25, 2023Updated 3 years ago