OpenExSys_NoC a mesh-based network on chip IP.
☆20Dec 1, 2023Updated 2 years ago
Alternatives and similar repositories for OpenExSys_NoC
Users that are interested in OpenExSys_NoC are comparing it to the libraries listed below
Sorting:
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 3 months ago
- An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.☆35Updated this week
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆26Mar 13, 2025Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- ☆13Jul 28, 2022Updated 3 years ago
- RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer…☆29Jul 12, 2024Updated last year
- PULP C910, a superscalar out-of-order RISC-V core adapted from T-Head's openC910 (Alibaba Group) and integrated into the PULP ecosystem w…☆16Jun 11, 2025Updated 9 months ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- ☆22Feb 22, 2020Updated 6 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- ☆20May 13, 2025Updated 10 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Mar 15, 2026Updated last week
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated 3 weeks ago
- ☆17Dec 21, 2020Updated 5 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Mar 17, 2022Updated 4 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- ESnet general-purpose FPGA design library.☆14Updated this week
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- tpu-systolic-array-weight-stationary☆25May 7, 2021Updated 4 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆30Nov 13, 2025Updated 4 months ago
- ☆21Jun 26, 2025Updated 8 months ago
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆22Jan 13, 2025Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆37Dec 22, 2023Updated 2 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆18Feb 27, 2025Updated last year
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- xkDLA:XinKai Deep Learning Accelerator (RTL)☆39Jan 15, 2024Updated 2 years ago
- ☆13Jun 4, 2020Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆182Dec 14, 2019Updated 6 years ago