Alternatives and similar repositories for OpenExSys_NoC

Users that are interested in OpenExSys_NoC are comparing it to the libraries listed below

• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆17Updated 2 years ago
• donlon / axi-dma-controller
  Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.
  ☆13Updated last year
• Aquaticfuller / OpenExSys_CoherentCache
  OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.
  ☆20Updated 9 months ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆13Updated 10 years ago
• pulp-platform / hier-icache
  ☆14Updated 10 months ago
• avikram2 / RISCVPipelinedProcessor
  Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…
  ☆14Updated 3 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 11 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆16Updated 9 years ago
• jiayi-wang98 / lpddr4_memory_controller
  ☆10Updated 3 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆22Updated last year
• CMU-SAFARI / MIG-7-PHY-DDR3-Controller
  A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.
  ☆11Updated 4 years ago
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 11 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆20Updated 4 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆15Updated 6 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated 2 months ago
• pulp-platform / axi_llc
  ☆33Updated last month
• pulp-platform / ace
  ☆20Updated 3 weeks ago
• Purdue-SoCET / atalla
  Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.
  ☆22Updated 3 weeks ago
• raiyyanfaisal09 / Router1X3_RTL_Design
  - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…
  ☆11Updated 6 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆21Updated 9 months ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 5 years ago
• efabless / EF_UART
  Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP
  ☆14Updated 10 months ago
• PacoReinaCampo / MPSoC-DMA
  Direct Access Memory for MPSoC
  ☆13Updated this week
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆19Updated 5 years ago
• hankshyu / TaskScheduler
  a hardware task scheduler design
  ☆10Updated 3 years ago