Aquaticfuller / OpenExSys_NoCLinks
OpenExSys_NoC a mesh-based network on chip IP.
☆18Updated 2 years ago
Alternatives and similar repositories for OpenExSys_NoC
Users that are interested in OpenExSys_NoC are comparing it to the libraries listed below
Sorting:
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆12Updated last year
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆18Updated 8 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 2 years ago
- ☆14Updated 9 months ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- ☆10Updated 3 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- ☆16Updated 6 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- ☆20Updated 3 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆18Updated 11 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆21Updated this week
- ☆17Updated 10 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- ☆11Updated 2 years ago
- Tensor Processing Unit implementation in Verilog☆11Updated 9 months ago
- Simple demo showing how to use the ping pong FIFO☆16Updated 9 years ago
- ☆13Updated 7 months ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 10 months ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆15Updated 3 years ago
- UVM Testbench for synchronus fifo☆19Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Verification IP for Watchdog☆12Updated 4 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 11 years ago