jha-lab / codebenchLinks
[TECS'23] A project on the co-design of Accelerators and CNNs.
☆20Updated 2 years ago
Alternatives and similar repositories for codebench
Users that are interested in codebench are comparing it to the libraries listed below
Sorting:
- ☆4Updated 4 years ago
- ☆17Updated 2 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆28Updated 4 months ago
- ☆25Updated 2 years ago
- ☆18Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- Open-source of MSD framework☆16Updated last year
- ☆72Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- ☆12Updated last year
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 10 months ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆46Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- ☆8Updated 2 years ago
- ☆34Updated 6 years ago
- ☆31Updated 2 months ago
- An HBM FPGA based SpMV Accelerator☆13Updated 11 months ago
- ☆36Updated 4 months ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- ☆27Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 2 years ago
- ☆17Updated 10 months ago
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆30Updated last year
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆30Updated 6 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year