A verilog implementation for Network-on-Chip
☆85Feb 3, 2018Updated 8 years ago
Alternatives and similar repositories for NoC-Verilog
Users that are interested in NoC-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆86Oct 25, 2014Updated 11 years ago
- CNN accelerator using NoC architecture☆18Dec 6, 2018Updated 7 years ago
- Network on Chip for MPSoC☆28Jun 16, 2026Updated last month
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- ☆42Apr 28, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆151Mar 19, 2018Updated 8 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆209Aug 27, 2022Updated 3 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆18Apr 12, 2020Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆12Jan 28, 2019Updated 7 years ago
- Netrace: a network packet trace reader☆16Jun 16, 2014Updated 12 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆66Jun 10, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆21May 30, 2023Updated 3 years ago
- ☆38Jun 3, 2024Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆184Dec 14, 2019Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- Network on Chip Simulator☆331Jun 9, 2026Updated last month
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- AXI Interconnect☆58Aug 20, 2021Updated 4 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- This is a collection of works and information on neuromorphic/ neuro-inspired computing.☆18Nov 16, 2019Updated 6 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- verification of simple axi-based cache☆19May 14, 2019Updated 7 years ago
- A Fast, Low-Overhead On-chip Network☆321Updated this week
- Synopsys Design compiler, VCS and Tetra-MAX☆20May 29, 2018Updated 8 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- HNoCS: Modular Open-Source Simulator for Heterogeneous NoCs.☆12Dec 12, 2022Updated 3 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- 🎞️ NoC router in Verilog with FIFO☆15Sep 1, 2022Updated 3 years ago
- ☆16Mar 18, 2025Updated last year
- This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 20…☆13Oct 20, 2020Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- A Chisel RTL generator for network-on-chip interconnects☆233Nov 7, 2025Updated 8 months ago