bakhshalipour / NoC-VerilogView external linksLinks
A verilog implementation for Network-on-Chip
☆81Feb 3, 2018Updated 8 years ago
Alternatives and similar repositories for NoC-Verilog
Users that are interested in NoC-Verilog are comparing it to the libraries listed below
Sorting:
- ☆82Oct 25, 2014Updated 11 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆144Mar 19, 2018Updated 7 years ago
- ☆40Apr 28, 2019Updated 6 years ago
- Network on Chip for MPSoC☆28Jan 27, 2026Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆198Aug 27, 2022Updated 3 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Apr 12, 2020Updated 5 years ago
- 🎞️ NoC router in Verilog with FIFO☆16Sep 1, 2022Updated 3 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Dec 15, 2025Updated 2 months ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆25Nov 2, 2015Updated 10 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Apr 20, 2014Updated 11 years ago
- ☆38Jun 3, 2024Updated last year
- A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.☆16May 30, 2023Updated 2 years ago
- The code of SpikingSSMs: Learning Long Sequences with Sparse and Parallel Spiking State Space Models☆22Apr 16, 2025Updated 10 months ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆180Dec 14, 2019Updated 6 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Feb 10, 2026Updated last week
- ☆18Apr 5, 2015Updated 10 years ago
- Implementation of the SHA256 Algorithm in Verilog☆38Jan 2, 2012Updated 14 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 6 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- ☆15Mar 18, 2025Updated 10 months ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Implementation of the PCIe physical layer☆60Jul 11, 2025Updated 7 months ago
- AXI Interconnect☆57Aug 20, 2021Updated 4 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- AXI X-Bar☆19Apr 8, 2020Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago