bakhshalipour / NoC-VerilogLinks
A verilog implementation for Network-on-Chip
☆77Updated 7 years ago
Alternatives and similar repositories for NoC-Verilog
Users that are interested in NoC-Verilog are comparing it to the libraries listed below
Sorting:
- ☆38Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆138Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆71Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆183Updated 3 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆108Updated 5 years ago
- ☆79Updated 11 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆95Updated 6 years ago
- ☆66Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆69Updated last year
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- ☆57Updated 6 years ago
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- ☆72Updated 9 years ago
- round robin arbiter☆77Updated 11 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆68Updated last week
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆182Updated last year
- AXI总线连接器☆105Updated 5 years ago
- 3×3脉动阵列乘法器☆48Updated 6 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago